DATA PROCESSING DEVICE AND PROGRAM

WIPO Patent Application WO/2014/080469

A1

A clock signal generation unit (104) shifts the phase of a reference operating clock signal so as to generate one or more phase-shifted clock signals. A frame processing unit (101) receives a synchronization frame. In addition, the frame processing unit (101) receives a correction frame, in which is included a correction value representing, in decimal representation, the time until a synchronization point, which is the timing from receiving a synchronization frame until performing time synchronization, as clock cycles of the reference operating clock signal. A clock signal selection unit (102), on the basis of a value of the fractional part of the correction value, selects one clock signal from among the reference operating clock signal and the phase-shifted clock signals. A signal generation output unit (110), at a time from receiving the synchronization frame until a rising edge of a clock pulse of a cycle corresponding to the value of the real part of the correction value, in accordance with the clock signal selected by the clock signal selection unit (102), generates a SYNC signal reporting arrival of the synchronization point, and outputs the generated SYNC signal.

JPS6040747	[Title of the Invention] Bit synchronization circuit
JPS62241435	SPLIT PHASE CODE DECODING CIRCUIT
JP3943677	EQUIPMENT FOR PERFORMING TIMER MANAGEMENT IN EQUIPMENT SYSTEM

TAKEUCHI KIYOFUMI (JP)

PCT/JP2012/080155

May 30, 2014

November 21, 2012

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MITSUBISHI ELECTRIC CORP (JP)
TAKEUCHI KIYOFUMI (JP)

H04L7/00

WO2012114517A1

2012-08-30

JP2011211673A	2011-10-20
JPH0983608A	1997-03-28

MIZOI, Shoji et al. (JP)
Shoji Mizoi (JP)

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