Title:
DATA PROCESSING METHOD AND DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/166337
Kind Code:
A1
Abstract:
Disclosed in the present application are a data processing method and device, for use in reducing the load hit latency when big-endian data format and little-endian data format mismatch. The method comprises: obtaining a read instruction sent by a processor instruction pipeline, wherein the read instruction comprises address information of first data to be read in an external memory of a cache, the read/write width of the cache is 2P bytes, and the number of bytes of the first data, i.e., K, is less than or equal to P; when the data format supported by the external memory mismatches the data format supported by the processor instruction pipeline, determining address information of second data in the cache according to the address information of the first data in the external memory, wherein the second data is data in third data and corresponding to the first data, and the third data is data obtained by converting a cacheline comprising the first data between big endian format and little endian format; reading 2P bytes of fourth data from the cache according to the address information of the second data in the cache; rotating the fourth data right by a first byte to obtain fifth data; and sending the second data in the fifth data to the processor instruction pipeline.
Inventors:
XU ZHITONG (CN)
SUN LU (CN)
XIONG LIWEN (CN)
CUI LUPING (CN)
CHEN JUNRUI (CN)
YU WEIWEI (CN)
LIH IULIN (CN)
SUN LU (CN)
XIONG LIWEN (CN)
CUI LUPING (CN)
CHEN JUNRUI (CN)
YU WEIWEI (CN)
LIH IULIN (CN)
Application Number:
PCT/CN2018/077026
Publication Date:
September 20, 2018
Filing Date:
February 23, 2018
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F9/38
Foreign References:
| CN102135941A | 2011-07-27 | |||
| CN104156323A | 2014-11-19 | |||
| US20040230765A1 | 2004-11-18 |
Attorney, Agent or Firm:
BEIJING ZBSD PATENT & TRADEMARK AGENT LTD. (CN)
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