Title:
DATA PROCESSING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2011/001486
Kind Code:
A1
Abstract:
Read-out processing (ST102 to ST111) is carried out on an ith designated block storing an ith divided data string (ST101). If the ith divided data string cannot be read out normally, read-out processing is sequentially carried out on an ith normal block storing the ith divided data string which is included in each of a plurality of groups of normal blocks (ST114). If the ith divided data string can be read out normally, it is determined whether reading-out of p divided data strings has been completed (ST112). If it is determined that the reading-out of the p divided data strings has not been completed, read-out processing is carried out on an i+1st designated block storing an i+1st divided data string following the ith divided data string (ST115).
Inventors:
TAKAHASHI TSUKASA
SEZAKI TOMOHISA
TSUBOI NOBUHIRO
MINO YOSHITERU
SEZAKI TOMOHISA
TSUBOI NOBUHIRO
MINO YOSHITERU
Application Number:
PCT/JP2009/006753
Publication Date:
January 06, 2011
Filing Date:
December 10, 2009
Export Citation:
Assignee:
PANASONIC CORP (JP)
TAKAHASHI TSUKASA
SEZAKI TOMOHISA
TSUBOI NOBUHIRO
MINO YOSHITERU
TAKAHASHI TSUKASA
SEZAKI TOMOHISA
TSUBOI NOBUHIRO
MINO YOSHITERU
International Classes:
G06F9/445; G06F12/00; G06F12/06; G06F12/16
Foreign References:
| JP2005215824A | 2005-08-11 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
Download PDF:
Previous Patent: PHOTOCURABLE HEAT-CURABLE RESIN COMPOSITION
Next Patent: TAPE CASSETTE AND TAPE PRINTER
Next Patent: TAPE CASSETTE AND TAPE PRINTER