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Title:
A DATA PROCESSING SYSTEM AND A METHOD FOR SYNCHRONIZING DATA TRAFFIC
Document Type and Number:
WIPO Patent Application WO2006059277
Kind Code:
A3
Abstract:
The invention relates to a data processing system and a method for synchronizing data traffic. The data processing system according to the invention comprises a conversion unit, which conversion unit is arranged to convert a first flow control scheme applied in a first sub-network into a second flow control scheme applied in a second sub- network. The conversion unit may cooperate with or be integrated with another component, for example a component which performs conversion of operating frequency between sub¬ networks (clock-domain crossing). For the correct functioning of flow control it is necessary that separate flow control schemes are used for respectively the first sub-network and the second sub-network. The conversion unit performs a conversion between these schemes. For example, if the flow control schemes are credit-based the conversion unit computes the correct amount of credits for the first flow control scheme, based on the amount of credits available in the second flow control scheme. If necessary, credit conversion is performed. The latter is necessary when the flit sizes are different in the first and second sub-network, for example. The conversion unit translates the credits from the second sub-network (which credits represent a certain amount of data elements) into credits for the first sub-network. The number of credits may be different in respectively the first and second sub-network, for the same amount of data elements.

Inventors:
GOOSSENS KEES G W (NL)
RADULESCU ANDREI (NL)
Application Number:
PCT/IB2005/053954
Publication Date:
October 12, 2006
Filing Date:
November 29, 2005
Export Citation:
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Assignee:
KONINKL PHILIPS ELECTRONICS NV (NL)
GOOSSENS KEES G W (NL)
RADULESCU ANDREI (NL)
International Classes:
G06F15/78
Foreign References:
US20040218531A12004-11-04
Other References:
RAJIT MANOHAR ET AL: "Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI", IEEE COMMUNICATIONS MAGAZINE, IEEE SERVICE CENTER, PISCATAWAY, US, vol. 39, no. 11, November 2001 (2001-11-01), pages 149 - 155, XP011091849, ISSN: 0163-6804
HYPERTRANSPORT CONSORTIUM: "Hypertransport-enable Product", 11 July 2004 (2004-07-11), XP002388867, Retrieved from the Internet [retrieved on 20060705]
HASAN S R ET AL: "Design constraints of a hypertransport-compatible network-on-chip", CIRCUITS AND SYSTEMS, 2004. NEWCAS 2004. THE 2ND ANNUAL IEEE NORTHEAST WORKSHOP ON MONTREAL, CANADA 20-23 JUNE 2004, PISCATAWAY, NJ, USA,IEEE, 20 June 2004 (2004-06-20), pages 269 - 272, XP010742507, ISBN: 0-7803-8322-2
MAS G ET AL: "Network-on-chip: the intelligence is in the wire", COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, 2004. ICCD 2004. PROCEEDINGS. IEEE INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 11-13 OCT. 2004, PISCATAWAY, NJ, USA,IEEE, 11 October 2004 (2004-10-11), pages 174 - 177, XP010736767, ISBN: 0-7695-2231-9
D ANDERSON, J TRODDEN: "HyperTransport Flow Control", INFORMIT.COM, 6 June 2003 (2003-06-06), XP002388670, Retrieved from the Internet [retrieved on 20060705]
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