Title:
DATA PROCESSOR
Document Type and Number:
WIPO Patent Application WO/2005/024625
Kind Code:
A1
Abstract:
A data processor enabling reduction of overhead of rounding with an efficient circuit constitution and enabling efficient improvement of the numeric operation accuracy of an information processor using a fixed-point calculating unit. The data processor comprises a processor including a shifter (10) having a right bit-shift calculation function and an ALU (50) having a carry-in function of adding one-bit data to the least significant bit when two numbers of input data are added, and a control unit (200) for controlling the processor by a single instruction. The shifter (10) has a rounding evaluation circuit (110) for outputting the data on the result of shift operation, performing rounding evaluation of the bit rounded down when data is right-bit-shifted and outputting one-bit data representing whether or not it is necessary to add “1” to the least significant bit of the shift calculation result. The ALU (50) handles one of the two number of input data as output data of the shifter (10) and handles the data used by the carry-in function as one-bit data outputted from the rounding evaluation circuit (110).
Inventors:
OCHIAI TATSUO (JP)
AKAHIRA OSAMU (JP)
AKAHIRA OSAMU (JP)
Application Number:
PCT/JP2003/010976
Publication Date:
March 17, 2005
Filing Date:
August 28, 2003
Export Citation:
Assignee:
HITACHI ULSI SYS CO LTD (JP)
OCHIAI TATSUO (JP)
AKAHIRA OSAMU (JP)
OCHIAI TATSUO (JP)
AKAHIRA OSAMU (JP)
International Classes:
G06F7/57; (IPC1-7): G06F7/00
Foreign References:
| JP2000010762A | 2000-01-14 | |||
| JPH08202530A | 1996-08-09 |
Attorney, Agent or Firm:
Tsutsui, Yamato (3F Azeria Bldg., 1-1, Nishi-shinjuku 8-chom, Shinjuku-ku Tokyo, JP)
Download PDF:
Previous Patent: PRINTING DIGITAL DOCUMENTS
Next Patent: SYSTEMS FOR THE IMPLEMENTATION OF A SYNCHRONIZATION SCHEMAS
Next Patent: SYSTEMS FOR THE IMPLEMENTATION OF A SYNCHRONIZATION SCHEMAS