Title:
DATA RECEPTION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2011/021357
Kind Code:
A1
Abstract:
Difference of a constant delay between a rising edge and a falling edge of a data signal can be reduced. A data reception circuit comprises an amplification circuit which amplifies and outputs a data signal which transmits data, a first delay circuit which delays the output from the amplification circuit in accordance with a first control signal and outputs as a first delay data signal, a second delay circuit which delays the output from the amplification circuit in accordance with a second control signal and outputs as a second delay data signal, and a data signal reproduction circuit which generates and outputs a reproduction data signal on the basis of an active edge of the first delay data signal and an active edge of the second delay data signal.
Inventors:
TAKEDA NORIAKI
Application Number:
PCT/JP2010/004944
Publication Date:
February 24, 2011
Filing Date:
August 05, 2010
Export Citation:
Assignee:
PANASONIC CORP (JP)
TAKEDA NORIAKI
TAKEDA NORIAKI
International Classes:
H03K5/1532; G06F12/00; G06F13/42; H03K5/13
Domestic Patent References:
| WO2002099810A1 | 2002-12-12 |
Foreign References:
| JPH01108809A | 1989-04-26 | |||
| JPH0332137A | 1991-02-12 | |||
| JP2001195884A | 2001-07-19 | |||
| JPH0856143A | 1996-02-27 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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