DC BRUSHED MOTOR DRIVE WITH CIRCUIT TO REDUCE DI/DT AND EMI

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is based on and claims priority to U.S. Provisional Patent Application Serial No. 60/952,334, filed on July 27, 2007 and entitled DC BRUSHED MOTOR DRIVE WITH CIRCUIT TO REDUCE DI/DT AND EMI, FOR MOSFET VTH DETECION, VOLTAGE SOURCE DETECTION AND OVERPOWER PROTECTION, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a new component for switching an inductive load powered at few kHz, e.g., a motor, a pump, a fan, etc., and more particularly to reducing the EMI and thus the size of an input filter.

[0003] Today in the automotive industry 80% of variable speed motor commands are made using a MOSFET drive in linear mode. This kind of drive dissipates a fraction of unused energy in the form of heat, about HOW for a 450W motor. A IOOW dissipated in the form of heat represents 0.1 liters per 100 Km or 0.1 L/h gas consumption (2 miles per gallon). With the Kyoto Protocol, automotive vendors have to find a way to reduce the CO ₂ emission and improve the yield of a drive motor. For that reason, a new solution: a 20 kHz switching drive, is now being explored. 20 kHz is not audible to the human ear. This solution can reach up to 90% yield, but can create conduction electromagnetic perturbation (EMI) due to high frequency coupling. To reduce the EMI of the input battery filter, the automotive vendors are forced to add a big input filter to a power switching circuit of the motor drive, thereby increasing the final price of the motor drive.

[0004] Figure 1 illustrates the most common solution used to reduce the EMI in a power switching circuit driving an inductive load. The power switching circuit includes high- and low-side transistors, e.g., MOSFET, series connected at a switching node Vs. The switching node driving a load. Figure 1 shows a source terminal of the high-side transistor Ql coupled at the switching node Vs to a cathode of a diode Q2 and an inductor Ll (the load) connected between the switching node Vs and ground. In accordance with that solution, resistor Rg is placed in a path of a current Igate providing PWM pulses to a gate terminal of the transistor Ql . The placement of resistor Rg at the gate terminal allows smooth injection of the current in the gate terminal. As shown in Figure 2, which illustrates gate to source and drain to source voltage and drain to source current when the transistor Ql is ON and OFF, the drawback of this solution is that the switching losses are maximal, therefore the transistor Ql heats up a lot.

[0005] Another way to reduce the EMI, as illustrated in Figure 3, was explored a few years ago. The main idea behind this method is to perform gate shaping, i.e., changing the gate profile over time. In particular, Figure 3 illustrates, in steps 1 and 2 pre-charging of a gate terminal of the transistor Ql to voltage Vth and to gate to source voltage ON Vgson at step 4 and the effect on load current I _load through the load Ll and the drain to source voltage Vds. This solution takes a huge step forward proving that the gate shaping works, and if it is well set up can reduce the EMI by 4. As voltage Vth value is not known in advance, a complicated loop must be developed to auto-adapt the circuit. After several cycles, pre-charge voltage Vprech to reduce and regulate the turn ON delay with an external consign.

[0006] However, applying the same principle for the turn OFF becomes complicated because the source voltage moves very quickly and it becomes very difficult to catch the right event at the right moment. Due to these difficulties an improved, more robust, and easier to manufacture system becomes necessary.

SUMMARY OF THE INVENTION

[0007] It is an object of the present invention to provide a gate driver that will reduce the EMI and minimize switching losses of the transistor of the power switching circuit.

[0008] Provided is a gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first transistor while free wheeling current is flowing in a second transistor of the switching stage, and controlling the dv/dt(ON) of the first transistor while a charge on the gate terminal is present; and upon receipt of an OFF pulse controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor, and controlling the di/dt(OFF) flowing in the first transistor while the gate to source terminal voltage equals the Vth.

[0009] Also provided is a gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver including a detection circuit for upon receipt of an ON pulse detecting voltage Vth, the gate driver pre- charging the gate terminal until gate to source terminal voltage equals Vth, a logic control circuit for controlling the di/dt(ON) flowing in the first transistor after receipt of an ON pulse while free wheeling current is flowing in a second transistor of the switching stage, and controlling the di/dt(OFF) flowing in the first transistor after receipt of an OFF pulse while the gate to source terminal voltage equals Vth; a first control circuit for controlling the dv/dt(ON) of the first transistor after receipt of an ON pulse while a charge on the gate terminal is present; and a second control circuit for upon receipt of an OFF pulse

controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor.

[0010] Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram showing a solution of reducing the EMI in a power switching circuit driving an inductive load where a resistor is placed in the path of the gate terminal;

[0012] Figure 2 is a timing diagram of signals in the switching circuit of Figure 1;

[0013] Figure 3 is a block diagram illustrating a method for reducing EMI using gate shaping;

[0014] Figure 4 is a graph showing a gate shaping profile for the switching circuit of Figure 1;

[0015] Figure 5 is a flowchart illustrating a synoptic diagram of a gate profile sequence;

[0016] Figures 6 A and 6B are block diagrams illustrating detection of voltage Vth at the low- and high-side MOSFET of the switching circuit of Figure 1, respectively;

[0017] Figure 6C is a timing diagram of the Vth detection circuit of Figures 6 A and 6B;

[0018] Figure 6D is a circuit diagram showing an implementation of Vth detection of Figures 6 A and 6B;

[0019] Figure 7A is a block diagram illustrating a principle of "End of diode conduction detector" circuit of the present invention;

[0020] Figure 7B is a timing diagram of the "End of diode conduction detector" circuit of Figure 7A;

[0021] Figures 7C and 7D are circuit diagrams showing implementations of the circuit of Figure 7 A;

[0022] Figure 8A is a circuit diagram illustrating a principle of "gate discharged to ground" circuit of the present invention;

[0023] Figure 8B is a timing diagram of the "gate discharged to ground" circuit of Figure 8A;

[0024] Figure 8C is a circuit diagram showing implementation of the circuit of Figure 8A;

[0025] Figure 9 A is a bloc diagram of the di/dt control driver of the present invention;

[0026] Figures 9B and 9C are circuit diagrams of an implementation of the di/dt control MOS gate driver of the present invention;

[0027] Figure 1OA is a block diagram of the Overpower Protection circuit of the present invention;

[0028] Figure 1OB is a timing diagram of the Overpower Protection circuit of Figure 1OA in normal condition;

[0029] Figure 1OC is a timing diagram of the Overpower Protection circuit of Figure 1 OA in short circuit condition;

[0030] Figure 1OD is a timing diagram of the of the Overpower Protection circuit of Figure 1OA in repetitive short pulses condition;

[0031] Figure 1 IA is a block diagram of the Overpower Protection circuit of the preferred embodiment of the present invention;

[0032] Figure 1 IB is a timing diagram of the of the Overpower Protection circuit of Figure 1 IA in normal condition;

[0033] Figure 11C is a timing diagram of the of the Overpower Protection circuit of Figure 1 IA in short circuit condition;

[0034] Figure 1 ID is a timing diagram of the of the Overpower Protection circuit of Figure 1 IA in repetitive short pulses condition; and

[0035] Figure 1 IE is a circuit diagram of an implementation of the Overpower Protection circuit of the preferred embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0036] The present invention is directed to a gate driver for managing internally controlled di/dt of a transistor, e.g., a MOSFET, by dynamically managing gate voltage. This di/dt trade-off is set internally to the gate driver to an optimum value between power dissipation (switching losses) versus noise (EMI). This feature allows a circuit designer to choose less EMI versus power. Most importantly, the present invention allows to not continue to rely on the closed loop but to find a way to detect all events needed to properly manage the gate shaping.

[0037] Since, as shown in Figure 4, every slope of gate voltage changes as a function of an event and not as a function of time, this profile sequence can be translated in to a synoptic diagram illustrated in Figure 5. Accordingly, as shown in Figures 4 and 5, the turn ON sequence includes the following steps: After receipt by the MOSFET of an ON pulse, step 1 of the sequence enables passing of internal propagation time. Step 2 reduces turn ON delay by pre-charging the gate terminal of the MOSFET until it reaches voltage Vth, i.e., until gate to source voltage Vgs is equal Vth. Step 3 the current at the gate Igate of the MOSFET is controlled to control the di/dt(ON) flowing through the MOSFET until voltage at the source terminal Vs is at zero volt, indicating an end of free wheeling in the

diode Q2. At step 4, at the end of the gate being charged, the dv/dt(ON) of the MOSFET is controlled to reduce switching losses.

[0038] The turn OFF sequence of the MOSFET includes the following steps: After receipt by the MOSFET of an OFF pulse, step 5 enables passing of the internal propagation time. Step 6 the dv/dt(OFF) of the MOSFET is controlled to reduce switching losses until voltage at the source terminal Vs is at zero volt indicating the beginning of free wheeling in the diode Q2. In step 7, current at the MOSFET gate terminal Igate is controlled to control the di/dt(OFF) flowing through the MOSFET until the gate to source terminal voltage Vgs reaches Vth. At step 8, if the gate to source terminal voltage Vgs reaches zero volt, the gate discharge has ended and the MOSFET is prepared for a new cycle.

MOSFET's Vth DETECTOR

[0039] This section describes step 2 in the diagram of Figure 5. The challenge is to be able to detect voltage Vth at the MOSFET's gate terminal and when the source terminal reaches and passes by zero volt. A MOSFET's Vth detector circuit 10 is illustrated in Figure 6A, the circuit 10 detects voltage Vth, current sense MOSFET M2 is used, letting the output current image Isense flow in a resistor Rsense and using a comparator 12 to compare the voltage on the resistor Rsense and a reference voltage. If a voltage drop exists on the resistor Rsense, it means that a current flows in the current sense MOSFET M2. This also means that a small current Ids flows in the low-side main output MOSFET Q2, indicating that voltage Vth is reached.

[0040] The above makes it possible to compare the voltage drop on the resistor Rsense to the reference voltage, and thus give a two state output, for example "0" logic if the voltage Vgs of the current sense MOSFET M2 is smaller than voltage Vth and "1" if the voltage Vgs of the current sense MOSFET M2 is equal or greater than voltage Vth. Figure 6B shows detection of voltage Vth on the high side MOSFET Ql.

[0041] Figure 6C illustrates a timing diagram of the Vth detection circuit of Figures 6 A and 6B, showing the current Igate provided to gate terminals of the current sense MOSFET M2 and the high- or low-side MOSFETs Ql and Q2; gate to source voltage Vgs of the current sense MOSFET M2 and the drain to source current through the high- or low-side MOSFETs Ql and Q2; gate to source voltage Vgs of the high- or low-side MOSFETs Ql and Q2 and the current Isense through the resistor Rsense, as well as a voltage Vrsense on resistor Rsense. Finally, Figure 6C illustrates a CompOut signal generated by the comparator 12. Further, other possible applications of the described "MOSFET's Vth detector" scenario include "control of dead time" and "control of Tdon of two different power MOSFETs.

[0042] Further, Figure 6D illustrates a possible embodiment of a fast turn ON Gate pre-charge circuit diagram. The circuit includes a 40 mV Comparator for measuring Vth and a circuit for completely turning OFF the gate after di/dt control at turn OFF.

END OF DIODE CONDUCTION DETECTOR: SOFT DV/DT ON

[0043] This section describes step 4 in the diagram of Figure 5. During a free wheeling state, the source voltage is under OV (Vs = -Vf diode Q2). When the voltage at Vs rises up after free wheeling, Vs crosses zero volts quickly. To detect this short instance a very quick comparator is needed. But to make a measurement so close to the power supply rail it would be necessary to create a negative charge pump to have enough voltage range to be able to compare a voltage to a reference. What is provided is a simple solution to avoid creating a negative charge pump, using few components to make a highly responsive circuit.

[0044] As shown in Figure 7A, diode Dl is polarized by a resistor Rl, so the transistor Ml gate sees Vs+Vf _D i. When Vs+Vf _D i is greater than Vth _M i, the transistor Ml turns ON and lets flow current IO to create a voltage drop on a resistor R2 high enough to turn ON the transistor M3. This, as an effect to let flow "I_High_On" in the power MOSFET Ql. A timing diagram of the "End of diode conduction detector" is shown in

Figure 7B. Further, other possible applications of the described "End of diode conduction detector" scenario include High frequency synchronous rectification, dv/dt control driver.

[0045] Further, Figures 7C and 7D illustrate possible embodiments of the end of diode conduction detector circuits.

GATE DISCHARGE TO GROUND: SOFT DV/DT OFF

[0046] This section describes step 6 in the diagram of Figure 5. During this phase, the source (Vs) falls to ground very quickly, so it is very difficult to catch the instant where the source crosses zero volts. Moreover, if the circuit misses the zero cross, the Ids current will go down too quickly and generate EMI perturbation. That is why it is necessary to find a way to be sure to never miss this event. And this is exactly what the "gate discharge to ground" circuit, illustrated in Figure 8A, does controlling dv/dt.

[0047] During the 1st turn-OFF phase (see step 6 in the synoptic of Figure 5) the power MOSFET M2 is fully ON (Vs=Vdd) and the "gate discharge to ground" circuit is enabled. As Vs is tied to Vdd, VgsMl is greater then VtIi _M i so, Ml behaves as a switch with the negligible resistor in series. Thus, Igate=I_high_OFF+I_low_OFF and the source falls. The more the source falls to ground the more Ml is pinched, until complete shutdown when the Vs-Ground=Vth _M i. This creates a full and smooth control of the Vs voltage, as shown below, since there is no nonlinearity is the gate discharged current. A timing diagram of the "gate discharge to ground: soft dv/dt OFF" is shown in Figure 8B. Further, other possible applications of the described "gate discharge to ground: soft dv/dt OFF" scenario include High frequency synchronous rectification, dv/dt control driver.

[0048] The described gate discharge to ground creates a soft "S" shape signal, which can be used in other designs for dv/dt control. In such dv/dt control driver, this "S" shape signal helps avoid voltage discontinuity and thus has an effect of reducing EMI when the load is far from the driver.

[0049] Further, Figure 8C illustrates a possible embodiment of the gate discharge to ground circuit.

DI/DT CONTROL MOS GATE DRIVER

[0050] Figure 9A illustrates a diagram of a circuit 1 of one embodiment of the present invention including a logic control block that receives input of an ON/OFF signal, a Fast ON signal, a signal indicating detection of voltage at the switching node provided by the detection circuit 10, and a signal provided by a comparator 34 indicating if voltage at the switching node Vs is larger or smaller than a reference voltage mV and providing di/dt and dv/dt ON and OFF signals for controlling the circuit. In particular, the di/dt(ON) signal of the logic control circuit 20 controls a switch 22 to connect/disconnect low ON current source I_low_on to the gate of the power transistor Ql. The dv/dt(ON) signal controls a switch 24 to connect/disconnect high ON current source I_high_on to the gate of the power transistor Ql. Pre-charge signal Pre_ch controls a switch 26 to connect/disconnect pre-charge current source I_prech to the gate of the power transistor Ql. Discharge signal Dis_ch controls a switch 28 to connect/disconnect discharge current source I_disch to the gate of the power transistor Ql. The di/dt(OFF) signal of controls a switch 30 to connect/disconnect low OFF current source I low off to the gate of the power transistor Ql. The dv/dt(OFF) signal of controls a switch 32 to connect/disconnect high OFF current source I_high_off to the gate of the power transistor Ql.

[0051] The circuit 1 of Figure 9A also includes a charge pump diode 36 and a bootstrap diode connected to the high ON and low ON current sources. These two diode create an OR gate and allow the driver to operate at 100% Duty Cycle, thus, no bootstrap capacitor refresh is needed. When the bootstrap capacitor is fully discharged, a charge pump helps to keep the gate terminal 6 V over Vbat (Figures 1 and 6B).

[0052] Figures 9B and 9C are circuit diagrams of one implementation of the MOS gate driver, which provides the di/dt and dv/dt ON and OFF signals based on following logic control equation:

Pre _ ch = ON/OFF • Endjprech • Fast(OFF) di I dt(ON) = ON I OFF • Fast(OFF) dv I dt(ON) = ON I OFF • Vs _ Iv • Fast(OFF) di I dt(OFF) = ON I OFF + Fast(OFF) dv I dt{OFF ) = (ON I OFF • Vs _ Iv) + Fast {OFF ) Dis _ ch = ON/OFF • End_prech • Fast(OFF)

OVER POWER PROTECTION

[0053] During the turn ON or the turn OFF phase (linear mode), the current feedback is not available (Vs < Vss). So it is not possible to use this feature to protect the MOSFET against the over current. The di/dt control allows for a development of a new kind of circuit to protect the MOSFET during the turn ON phase against an over current condition.

[0054] For example, if the di/dt value is set up at 20 Amps by microsecond, the current in the MOSFET can be estimated just by measuring the time that the source takes to go up to Vdd. In the present case, after 3 μs if the signal Vds_075v is not present (the MOSFET is not fully ON, Vs far away from Vdd), it means that the current in the load is up to 60 amps (20A/μs * 3μs = 60A). Considering, this value too high for the specific application, the MOSFET must be turned OFF immediately, to avoid the part heating up too much and blowing-up.

[0055] The present system protects against all conditions which lead the MOSFET to be in linear mode (like a short duty cycle, short circuit, bootstrap capacitor disconnected) and keeps memory of the dissipated power stored during several successive turn-ON endeavors. The system reflects the power of switching losses, and protection can be

provided very close to the maximum power dissipation, allowing the application to operate close to maximum power without a degrading performance.

[0056] Figure 1OA illustrates a circuit diagram of principle of the Overpower Protection circuit in which "End_prech & Vds close to Vdd" means that the MOSFET' s driver controls the Ids slope, since the Vth has been reached (End_prech = 1). Normal, short circuit, and repetitive short pulses conditions are considered below.

[0057] In normal condition a capacitor Ctp is charged with a current I Ch, which is proportional to Vds, whilst the signal End_prech is up and until the MOSFET is fully ON (Vds close to Vdd). When the MOSFET is fully ON, the capacitor Ctp is discharged via a resistor Rpkg, which represent the Rth. Voltage Vctp did not reach Vref so, Ovp signal stays low. The timing diagram of the Overpower Protection circuit in normal condition is illustrated in Figure 1OB.

[0058] In short circuit condition the current source Ich C is activated and charges the capacitor Ctp until the voltage Vctp reaches the reference voltage Vref, since the Vs is bolted to ground. At this moment, Ovp signal rises up to flag the maximum switching losses it is allowed to reach. The timing diagram of the Overpower Protection circuit in short circuit condition is illustrated in Figure 1OC.

[0059] In short pulses condition, the MOSFET has not enough time to fully turn-ON, so during each short pulse it works in linear, and heats up a lot. As the source never goes up to Vdd the capacitor Ctp is never reset by Sl, but it is slowly discharged by resistor Rpkg. This resistor represents the thermal resistance of the package. So if the pulse frequency is too high, the capacitor never Ctp discharges completely (Rpkg), and pulse by pulse voltage Vctp goes closer and closer to reference voltage Vref. The timing diagram of the Overpower Protection circuit in repetitive short pulses condition is illustrated in Figure 1OD.

OVER POWER PROTECTION - PREFERRED EMBODIMENT

[0060] The above-described circuit does not take into account turn-OFF switching losses. But the preferred embodiment described below protects against the short circuit, because the probability to have a short circuit exactly during turn-OFF is very low and even if it append the MOSFET will sustain the power and the fault will automatically be detected at the next turn ON. This embodiment, illustrated in Figure 1 IA, where "End_prech & ON" means that the MOSFET is in its Turn-On phase (In=I) and that the driver control the Ids slope, since the Vth has been reached (End_prech = 1) is explained here under. Normal, short circuit, and repetitive short pulses conditions are considered.

[0061] In normal condition the current source Ich_C is activated and charges capacitor Ctp until the MOSFET is fully ON (Vds close to Vdd). At this moment Sl is closed and capacitor Ctp is discharged, voltage Vctp did not reach reference voltage Vref so, Ovp signal stays low. The timing diagram of the Overpower Protection circuit in normal condition is illustrated in Figure 1 IB.

[0062] In short circuit condition the current source Ich C is activated and charges capacitor Ctp until voltage Vctp reaches reference voltage Vref, since the Vs is bolted to ground. At this moment, Ovp signal rises up to flag the maximum switching losses it is allowed to reach. The timing diagram of the Overpower Protection circuit in short circuit condition is illustrated in Figure 11C.

[0063] In short pulses condition, the MOSFET has not enough time to fully turn-ON, so during each short pulse it works in linear, and heats up a lot. As the source never goes up to Vdd capacitor Ctp is never reset by Sl, but it is slowly discharged by resistor Rpkg. This resistor represents the thermal resistance of the package. So if the pulse frequency is too high, the capacitor never discharges completely (Rpkg), and pulse by pulse voltage Vctp goes closer and closer to reference voltage Vref. The timing diagram of the Overpower Protection circuit in repetitive short pulses condition is illustrated in Figure HD.

[0064] An implementation of the Overpower Protection circuit of the preferred embodiment is illustrated in Figure 1 IE.

[0065] Other possible applications of the circuit of the preferred embodiment include Control of the power dissipated and therefore the temperature variation during normal operation and thus increase the reliability of the component during a fault mode. This protection will also work to protect a MOSFET located far away from the driver.

[0066] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention not be limited by the specific disclosure herein.