A known converter of this type is disclosed in EP-A-0759654, which describes a switching power converter which comprises a transformer assembly including primary and secondary windings, and first and second choke windings intended to store energy. On the primary side, there are provided a pair of switching circuits respectively coupling the first and second choke windings to the primary winding. These switching circuits operate alternately during a switching cycle to provide a continuous output voltage and current from the secondary side.

The present invention seeks to provide an improved converter over that described in EP-A-0759654, in particular in the area of the primary switching circuitry.

In accordance with the invention, there is provided a DC-DC converter having input terminals for an input DC voltage and output terminals for an output DC voltage, a transformer assembly comprising first primary and secondary choke windings, second primary and secondary choke windings, and main primary and secondary windings, and switching circuitry for controlling the operation of the converter, said converter being characterised in that the three primary windings are directly connected in series to form a loop including a first connection by which the first primary choke winding is connected to one end of the main primary winding, a second connection by which the other end of the main primary winding is connected to one end of the second primary choke winding, and a third connection by which the other end of the first primary choke winding is connected to the other end of the second primary choke winding, in that said switching circuitry comprises a first switching circuit connected from said first connection to one of said input terminals and a second switching circuit connected from said second connection to said one of said input terminals, and in that said third connection is connected to the other of said

input terminals.

The three windings are directly connected together in order to avoid losses occasioned by the use of reactance elements such as the capacitors which are used at the first and second connections in the converter described in EP-A-0759654.

Each of said first and second switching circuits comprises first switch means for switching current from the input terminals into its adjacent primary choke winding in an initial phase of operation and second switch means for switching current from said adjacent primary choke winding to a storage means in the next phase of operation. The choke windings are designed to store energy so that energy stored in the primary choke windings in said first phase is available to pass to said storage means in the second stage. Preferably the first and second switching means are both constituted by switching transistors each of whose control electrodes are fed by a pulse switching waveform generated by a switching generator, well known in the art. The switching waveforms are such as to render the switching transistors ON (conductive) or OFF (non-'conductive) in a repeating sequence each of which contains four phases:- 1) A first phase in which current is taken from an input source connected across said input terminals and applied to the first primary choke winding and, at the same time, energy stored in said second storage means (in the previous sequence) is transferred to the main primary winding.

2) A second phase in which energy stored in the first primary choke winding in phase (1) is transferred to said storage means; 3) A third phase in which current is taken from the input source and applied to the second primary choke winding and, at the same time, energy stored in said first storage means is transferred to the main primary winding; 4) A fourth phase in which energy stored in the second primary choke winding in phase (3) is transferred to said storage means Preferably said storage means comprises a first storage means connected to the first switching circuit, and a second storage means

connected to the second switching circuit, which storage means are each constituted, for example, by a capacitor. Means are provided for connecting the first and second storage means in such a way that, during phases 2 and 4, they charge together. For example, if the first and second storage means are constituted by capacitors, the capacitors can be connected in parallel during phases 2 and 4.

During phases 1 and 3, however, the first and second storage means are isolated from one another and take it in turns to transfer energy to the main primary winding: for example, during phase 1, the first storage means may transfer energy to the main primary winding, whilst during phase 3, the second storage means transfers energy to the main primary winding.

The windings are preferably all wound on a common core, for example of ferrite material, which has three limbs : a first choke limb carrying the first primary and secondary choke windings, a second choke limb carrying the second primary and secondary choke windings and a main limb carrying the main primary and secondary windings. The limbs are joined in such a way that the magnetic flux in the main limb is the summation of the magnetic flux in the choke limbs, i. e.

¢2=¢3+ ¢1 where ¢2 iS the magnetic flux in the main limb (Pl is the magnetic flux in the first choke limb ¢3 is the magnetic flux in the second choke limb Preferably each of the choke limbs contains an air gap for the purpose of energy storage, as is well known.

Since each pair of primary/secondary windings is carried on a common limb, each pair of windings is subject to a common magnetic flux.

This in turn means that the voltage induced in the secondary winding is related to that of the primary winding as follows : -

where V2 is the voltage across the secondary winding V1 is the voltage across the primary winding N1 is the number of primary turns N2 is the number of secondary turns In order that the invention may be better understood, several embodiments thereof will now be described by way of example only, and with reference to the accompanying drawings in which:- Figure 1 is a circuit diagram showing an embodiment of a converter according to the invention; Figures 2 to 4 are circuit diagrams corresponding to that of Figure 1, but each showing a respective phase of its operation; Figure 5 is a waveform diagram illustrating the operation of the circuit of Figures 1 to 4; Figure 6 is a circuit diagram illustrating a modification in the circuit of Figures 1 to 4; and Figure 7 is a circuit diagram similar to Figure 1, but showing a further embodiment.

Referring to Figures 1 to 4 there is illustrated an embodiment of a converter according to the invention. Each of Figures 2 to 4 show different phases of operation of the circuit of Figure 1.

The circuit comprises a transformer assembly 1, together with primary circuitry and secondary circuitry respectively associated with the primary and secondary of the transformer, and respectively connected to positive and negative input terminals 2,3 for the application of an input DC voltage Vs, and positive and negative output terminals 4,5 across which the DC output voltage Vout is developed. It will be understood that the left and right positive input terminals 2 are connected together.

The primary of the transformer assembly 1 has three windings: a main primary winding TX1-P, and choke windings L1-P and L2-P. The secondary of the transformer assembly likewise has three windings: a main secondary winding TX1-S associated with winding TX1-P, a first

choke winding L1-S associated with winding L1-P and a second choke winding L2-S associated with winding L2-P. The transformer assembly comprises a ferrite core 6 which is illustrated diagrammatically in Figures 2 to 4. From these drawings, it can be seen that each pair of primary and secondary windings is wound about a common limb of the core. About a central limb 7 of the core are wound the main primary and secondary windings TX1-P and TX1-S ; around a first outer limb 8 of the core are wound the first primary and secondary choke windings L1-P and L1-S and around a second outer limb 9 of the core are wound the second primary and secondary choke windings L2-P and L2-S.

The three limbs 7,8 and 9 of the core extend between respective bridging limbs 10,11 and it will be noted that an air gap 12,13 exists in each of the outer limbs for the purpose of energy storage.

The three primary windings L1-P, TX1-P and L2-P are connected together in series to form a loop. To complete the loop, the left and right- hand positive input terminals 2 are connected together. As will be explained, input current flows either through choke winding L1-P or L2-P, depending upon the phase of operation. The left hand and right hand input terminals 3 are likewise connected together, via a common line 14.

As shown in Figure 1, a first switch Q1 is connected from the line joining windings L1-P and TX1-P to the common line 14. A second switch Q2 is connected from the line joining windings L2-P and TX1-P to the common line 14. Connected in parallel with switch Q1 is a series connection of a third switch Q3 and a capacitor C1 ; connected in parallel with switch Q2 is a series connection of a fourth switch Q4 and a capacitor C2. Each of these switches are controlled by means (not shown, but well known in the art) to open and close the switches so as to control operation of the circuit, as will be explained. In practice, it is likely that the switches Q1 to Q4 will be realised by switching transistors such as the MOSFETs S1 to S4 shown in Figures 2 to 4. The gates of each of the MOSFETs S1 to S4 is connected to circuitry (not shown) which supplies a series of pulse waveforms suitable to switch the MOSFETs on and off as required. The

MOSFETs S3, S4 are each connected in series with their respective capacitors C1, C2, with the drain of each MOSFET connected to the positive side of the respective capacitor. It should be noted that these MOSFETs switch at near-zero voltage.

The secondary windings L1-S, TX1-S and L2-S are also connected in series in a loop, the connection between windings L1-S and L2-S being connected to the positive output terminal 4. A switching diode D1 is connected from the line joining windings L1-S and TX1-S to a common line 15 connected to the negative output terminal 5; similarly, a switching diode D2 is connected from the line joining windings L2-S and TX1-S to the common line 15. The diodes D1 and D2 could be replaced by alternative switching devices, such as MOSFETs. A smoothing capacitor C3 is connected across the output terminals 4,5.

The operation of the circuit will now be described with reference to Figures 2 to 4 which each illustrate a respective phase in the operation of the circuit. In the following explanation, each of the primary windings has the same number N1 of turns, and each of the secondary windings has the same number N2 of turns. Note that all of the primary windings have the same number of turns and all of the secondary windings have the same number of turns. The primary to secondary turns ratio can however vary.

The operation proceeds in a push-pull manner through a repeating sequence of 4 phases, these phases being controlled by pulse switching waveforms applied to the gates of the respective switching transistors S1 to S4. Figures 5 C to F show the switching waveforms applied to the gates of switching transistors S1, S3, S2 and S4 respectively. It will be noted from Figures 5C to 5F that the gate drive for transistor S3 is the inverse of that for transistor S1 ; similarly the gate drive for transistor S4 is the inverse of that for transistor S2. For convenience in explanation, all of the phases P1 to P4 are shown in Figure 5 as being of equal period; however, in practice, this may not necessarily be the case. The period P1 + P2 = P3 + P4 is constant and is defined by the frequency of operation of the controller chip. However, the pulse width modulation can vary the period of phase 1

and phase 3 with a corresponding modification to phases 2 and 4 to maintain the fixed frequency of operation. The individual phases will now be described as follows :- Phase 1 During phase 1, illustrated in Figure 2, transistors S1 and S4 are ON (conducting) and transistors S2 and S3 are OFF (non-conducting). Thus the primary choke winding L1-P is effectively connected across the input terminals and thus receives a voltage Vs across it. This generates a magnetic flux +1, proportional to the applied voltage Vs, in the outer limb 8 and energy is stored in the corresponding air gap 12. The generated magnetic flux in turn links with the secondary choke winding L1-S to establish a voltage across it of Vs (N2/N1) in the direction indicated by the arrow.

Also during phase 1, the energy stored in the gap 13 of outer limb 9 during previous phase 3 (see below) induces a voltage Vsx across primary choke winding L2-P. The voltage is clamped at this level by the forward biasing of diode D2-see below.

During an earlier phase (phase 4 of the previous cycle, to be described below), the capacitor C2 has been charged to a voltage of Vs (1 + X), where % is the ratio of the ON time to the OFF time of each of the transistor switches Q1 and Q2.

Since transistors S1 and S4 are ON, the voltage across capacitor C2 is applied directly across the main primary winding TX1-P which establishes a magnetic flux (D2 in the central limb 7 of the core. This flux links with the main secondary winding TX1-S to induce a voltage of Vs (1+#) (N2/N1) in the direction indicated by the arrow.

The summation of the flux in all the limbs must equate to zero, i. e.: (fs = 1 + vs where (D3 is the magnetic flux in the outer limb 9.

As mentioned above, there is energy stored in gap 13 from the previous phase 3, and this stored energy contributes to the flux in outer limb 9. Thus, whilst it is true that all the flux has to summate to zero, the

flux in limb 9 is not solely established by this summation, but also by the energy storage in gap 13.

Substituting: Vs (1 + %)/N1 = Vs + (P3 Therefore: #3=Vs#/N1 The flux #3links with the secondary choke winding L2-S to induce a voltage ofVs# (N2/N1) in the direction indicated.

On the secondary side, diode D2 is forward biased and thus applies the voltage Vs% (N2/N1) of the secondary choke winding L2-S across the output terminals 4,5. Meanwhile, diode D1 is reverse biased and the summation of the induced voltage across the windings L1-S and TX1-S is also applied across the output terminals i. e.:- Vo=Vs (1 + x) (N2/Ni)-Vs (N2/Ni) =Vsx (N2/Ni) In other words, the voltage applied across the output terminals 4,5 due to the summation of windings L1-S and TX1-S is the same as the voltage across winding L2-S.

Phase 2 During phase 2, illustrated in Figure 3, transistors S1 and S2 are OFF and transistors S3 and S4 are ON. With transistor S1 turned OFF, the primary choke winding L1-P is removed from its source of power (Vs) and the flux in the outer limb 8 starts to collapse. The collapsing flux induces a voltage Vs% in the primary choke winding L1-P and the voltage is effectively clamped at this level by the forward biasing of diode D1-see below-and this charges up the capacitor C1, via the now-conducting transistor S3 and the source Vs, to a value of Vs (1 + X). In the same way, from phase 4 of the previous cycle (see below) the capacitor C2 is also charged up to a voltage of Vs (1 + x) via the now-conducting transistor S4 and the source Vs. It will be noted that, in both cases, current is drawn through the source Vs during this phase, as represented in Figure 5B,

which shows the waveform of the input current.

The collapsing flux in the two outer limbs 8,9 also induces a voltage of Vs% (N2/N1) across each of the secondary choke windings L1-S and L2-S, in the directions indicated.

Meanwhile, the magnetic flux (Pl, (D3flowing in the outside limbs 8,9 cancels in the central limb 7 so that substantially zero flux <) flows in the central limb. Thus no voltage is induced in the main secondary winding TX1-S.

In these circumstances, both diodes D1 and D2 in the secondary circuit are forward biased, thus effectively shorting the main secondary winding TX1-S, and applying the two secondary choke windings in parallel across the output terminals 4,5. The voltage at the output terminal during phase 2 is accordingly Vs% (N2/Ni)-i. e. the same as in phase 1.

The shorting of the main secondary winding TXI-S reflects through to the main primary winding TXI-P which, during phase 2, acts as a dead short. Bearing in mind that, during phase 2, the transistors S3 and S4 are both ON, this in turn means that the capacitors C1 and C2 are effectively connected in parallel with one another.

Phase 3 During phase 3, illustrated in Figure 4, transistors S2 and S3 are ON and transistors S1 and S4 are OFF. The situation is thus very similar to that of phase 1, except that it is the primary choke winding L2-P that is connected across the input terminals and thus receives a voltage Vs across it. This generates a magnetic flux #3, proportional to the applied voltage Vs, in the outer limb 9 and energy is stored in the corresponding air gap 13.

This in turn generates a voltage of Vs (N2/N1) in the secondary choke winding L2-S, by the same mechanism as described above. Meanwhile, the current in primary choke winding L1-P decays to a value insufficient to maintain the secondary output current and the voltage Vs (1 +X) stored across capacitor C1 from phase 2 begins to be applied via the now- conducting transistor S3 across the main primary winding TX1-P which in turn induces a voltage of Vs (1 +%) (N2/N1) in the main secondary winding

TX1-S, by the same mechanism as described above.

As before #2=#1+#3 Vs (1 + X)/Ni = Vs/Ni + q) 1 Therefore: (D VsX/N 1 In the secondary circuit, the diode D1 is forward biased, whilst the diode D2 is reverse biased. Thus the secondary choke winding L2-S applies its voltage Vs% (N2/N1) directly to the output terminals 4,5, whilst the voltage outputs of the other two secondary windings, L1-S and TX1-S, are summed to also apply a voltage ofVs#(N2/N1) across the output terminals.

It will thus be seen that the output terminals receive the same voltage in phase 3 as in phases 1 and 2.

Phase 4 This phase is identical to phase 2 and is illustrated in Figure 3.

During this phase the capacitors C1 and C2, effectively connected in parallel, and are each charged up to a voltage of Vs (1 +%) due to the collapsing flux in the respective outer limbs 8,9. In addition the diodes D1, D2 are both forward biased, thus effectively shorting the main secondary winding TX1-S and applying the voltage Vs% (N2/N1) from the two secondary choke windings L1-S and L2-S across the output terminals 4,5.

The output voltage Vo in all four phases of operation is thus the same, thus providing a continuous output voltage and current from the secondary side.

Referring now to Figure 7 there is shown a circuit equivalent to that of Figure 1, but showing a second embodiment of the invention having modified circuitry on the secondary side of the transformer 1.

In the embodiment of Figure 7, the two secondary choke windings L1-S and L2-S are connected in series by the common line 15 which in turn is connected to the output terminal 5. The series-connected secondary choke windings are themselves connected in parallel with the main secondary winding TX1-S and switching diodes D3, D4 are connected from

the respective ends of the main secondary winding TX1-S to a common line 16 which is in turn connected to the output terminal 4.

The circuit of Figure 7 gives the same results as that of Figure 1, and the detailed operation will be apparent to those skilled in the art, based on the explanation given above. As before, the diodes D3 and D4 can be replaced by alternative switching devices such as MOSFETS.

The above described design, whilst operating in a comparable manner to the converter described in EP-A-0759654, possesses a number of circuit differences on the primary side which fundamentally change the manner of operation, and lead to improved performance. These differences will be apparent from the above description, when compared with that in EP-A-0759654, but are discussed in more detail as follows : - 1. In the converter described in EP-A-0759654, the three primary windings of the transformer assembly are not connected directly, as in the present design, but are connected via capacitors C1, C2. Thus, in the known design, much of the input power has to flow through one or the other of capacitors C1 or C2, thus reducing efficiency. In the present design, the choke windings in the primary circuit are directly connected to either end of the main primary winding while the capacitors are effectively connected in parallel with the two switches Q1 and Q2.

2. During phases 2 and 4 of the operation of the converter described in EP-A-0759654, the switches Q1 and Q2 are both OFF, and diodes D1 and D2 in the primary circuit are both forward biased. The primary circuit capacitors C1, C2 are charged to a voltage of Vs (1 +%) and, once charged to this voltage, they are effectively out of circuit because there is no discharge route for either capacitor. For example, in a subsequent phase of operation, in which switch Q1 is ON and Q2 is OFF (phase 1), the positive (left hand) plate of capacitor C1 is connected to the negative rail via switch Q1. Primary diode D1 blocks the discharge path for capacitor C1 with the result that capacitor C1 charges to a peak value, after which it becomes immaterial to the functioning of the circuit. This also means that the input current is not continuous in nature, but flows only during the periods when

switches Q1 and Q2 are ON. Figures 5A and 5B compare the input current waveforms for the converter described in EP-A-0759654 (Figure 5A) with that of the converter of the present invention (Figure 5B). It can immediately be seen that the input current for the converter of the present invention varies little over time, compared with the pulsed nature of the input current waveform for the prior art converter.

3. Following on from (2) above, it will further be seen that, during phase 1 of the operation of the converter of the present invention, the charge on capacitor C2 appears directly across the main primary winding TX1-P which in turn transfers energy from primary to secondary. Likewise, in phase 3, the charge on capacitor C1 appears across the main primary winding TX1-P, with the same result. Because of the continuous nature of the input current (see Figure 5B), the peak currents (Ipk) are significantly smaller than those in the converter described in EP-A-0759654), leading to a reduced requirement for input filtering. In addition, the stress on the Mosfets is significantly reduced, resulting in a corresponding increase in efficiency and reliability.

4. In order for the converter described in EP-A-0759654 to operate with a continuous input current, the primary-side diodes D1, D2 could be replaced by MOSFETs. However, in order to drive these MOSFETs, a negative supply has to be derived due to the fact that when switch Q1 is switched ON, the positive plate of capacitor C1 is taken to the negative rail and a voltage-Vs (l +y,) appears across the anode of diode D2 (or the source of the MOSFET replacement). Additional windings on the transformer assembly would have to be added to derive this more negative supply. By contrast, in the converter of the present invention such an additional supply may be derived with ease, and Figure 6 shows a suitable design using a diode D10 and regulator 20 to derive a supply Vaux. A capacitor C3 is used for smoothing. During the period that switch Q1 is ON (phase 1), the diode D10 conducts and voltage Vs appears at the input to the regulator 20. The regulator regulates the voltage down to the required level, and capacitor C3 stores the voltage between one phase 1 period and the next. For clarity only the primary part of the circuit is illustrated in Figure 6; the remainder of the circuit is as in Figure 1/Figure 7.