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Title:
DEAD TIME COMPENSATION USING AN ERROR VOLTAGE CALCULATION
Document Type and Number:
WIPO Patent Application WO/2019/028444
Kind Code:
A1
Abstract:
Systems and methods for controlling an electric motor are disclosed. The electric motor may be powered by a DC power source using an inverter, and may be used to power an electric vehicle. Error voltages, corresponding to average voltage loss over a switching period due to inverter switching dead time, can be calculated for each phase of the inverter. The error voltages may be converted to alpha and beta error voltages and used to generate duty cycle commands to drive the electric motor. Correction terms may further be applied to avoid unnecessary voltage increases at low phase currents and high modulation indices.

Inventors:
GRUBIC, Stefan (18455 S. Figueroa Street, Gardena, CA, 90248, US)
CAMPBELL, Mengwei, Li (18455 S. Figueroa Street, Gardena, CA, 90248, US)
Application Number:
US2018/045289
Publication Date:
February 07, 2019
Filing Date:
August 03, 2018
Export Citation:
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Assignee:
FARADAY&FUTURE INC. (18455 S. Figueroa Street, Gardena, CA, 90248, US)
International Classes:
B60L3/00; B60L15/20; H02P27/08
Attorney, Agent or Firm:
YOUNKINS, Karen et al. (Faraday&Future Inc, 18455 S. Figueroa StreetGardena, CA, 90248, US)
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Claims:
WHAT IS CLAIMED IS:

1. A computer-implemented method for controlling an electric motor and compensating for errors introduced by dead time of a pulse width modulation (PWM) scheme, the method comprising:

calculating a first average voltage per a switching cycle of the PWM scheme, the first average voltage representing an ideal voltage of the switching cycle without the dead time;

calculating a second average voltage per the switching cycle based on the first average voltage and the at least one correction term, the second average voltage representing an actual voltage of the switching cycle with the dead time;

calculating an error voltage per the switching cycle based on the first and second average voltages, the error voltage representing a drop or increase in the voltage due of the switching cycle to the dead time in the switching cycle;

generating a duty cycle command for driving the electric motor by compensating for the calculated error voltage; and

driving the electric motor by selectively actuating, based on the calculated duty cycle command, a plurality of switches of an inverter electrically connected to the electric motor.

2. The computer-implemented method of Claim 1, further comprising:

determining a correction term based on one or more operating conditions of one or both of the electric motor and inverter; and

using the correction term to compensate for the calculated error voltage.

3. The computer-implemented method of Claim 2, further comprising determining the at least one correction term as a function of a magnitude of a complex current vector.

4. The computer-implemented method of Claim 2, further comprising determining whether to use a fade-in multiplier or a fade-out multiplier for the at least one correction term.

5. The computer-implemented method of Claim 4, further comprising calculating the fade-in multiplier or fade-out multiplier over one fundamental period of the PWM scheme.

6. The computer-implemented method of Claim 4, further comprising determining to use the fade-out multiplier and determining a value of the fade-out multiplier based on factors representing a percentage of a duty cycle not equal to 1 or 0 over one fundamental period.

7. The computer-implemented method of Claim 1, further comprising calculating a phase error voltage for each phase of power to the electric motor, the phase error voltage computed based on the error voltage.

8. The computer-implemented method of Claim 7, further comprising, for each phase of power, calculating the phase error voltage based on a phase voltage in a stationary frame.

9. The computer-implemented method of Claim 7, further comprising, for each phase of power, multiplying the phase error voltage by a sign factor of a phase current of the phase of power, the sign factor of the phase current being equal to 1 if the phase current is greater than zero and equal to -1 if the phase current is less than zero.

10. The computer-implemented method of Claim 7, further comprising, for each phase of power, converting the phase error voltage to alpha and beta voltage commands using a Clarke Transformation.

11. The computer-implemented method of Claim 9, further comprising generating the duty cycle command for the inverter by at least, for each phase of power, using the alpha and beta error voltages to compensate original alpha and beta voltage commands.

12. The computer-implemented method of Claim 1, further comprising calculating the error voltage per the switching cycle by calculating a difference between the first average voltage and the second average voltage.

13. An electric vehicle comprising:

an AC electric motor;

an energy storage device configured to supply DC power;

an inverter configured to implement a pulse width modulation (PWM) scheme to convert the DC power into AC power for the AC electric motor, the inverter having a phase leg for each phase of the AC power, each phase leg comprising two switches electrically connected in series across the energy storage device, each phase leg electrically connected to one of the poles of the stator at a connection point between the two switches; and

a motor controller comprising processing circuitry configured to selectively control each switch of the inverter between on and off positions to drive the motor by at least:

calculating an error voltage for each phase leg corresponding to a loss of average voltage due to dead time over a switching period of the PWM scheme;

calculating alpha and beta error voltages corresponding to the calculated error voltages;

generating a duty cycle command for the inverter by compensating for the alpha and beta error voltages; and

driving the motor by selectively actuating the switches of the inverter based on the duty cycle command.

14. The electric vehicle of Claim 13, wherein the motor controller is further configured to multiply the alpha and beta error voltages by a correction term when generating the duty cycle command.

15. The electric vehicle of Claim 14, wherein the motor controller is further configured to calculate the correction term as a fade-in multiplier that reduces the alpha and beta error voltage contributions to the duty cycle command at low phase currents.

16. The electric vehicle of Claim 15, wherein the motor controller is further configured to calculate the fade-in multiplier as equal to a phase current magnitude divided by a predetermined threshold current when the phase current magnitude is less than the predetermined threshold current, and wherein the fade-in multiplier is equal to 1 when the phase current magnitude is greater than or equal to the predetermined threshold current.

17. The electric vehicle of Claim 14, wherein the motor controller is further configured to calculate the correction term as a fade-out multiplier that reduces the alpha and beta error voltage contributions to the duty cycle command at high modulation indices.

18. The electric vehicle of Claim 17, wherein the motor controller is further configured to calculate the fade-out multiplier as equal to a percentage of a fundamental cycle in which the duty cycle is not equal to 0 or 1.

19. The electric vehicle of Claim 14, wherein the motor controller is further configured to calculate the correction term as a multiplicative product of a fade-in multiplier and a fade-out multiplier, wherein the fade-in multiplier reduces the alpha and beta error voltage contributions to the duty cycle command at low phase currents, and wherein the fade- out multiplier reduces the alpha and beta error voltage contributions to the duty cycle command at high modulation indices.

20. The electric vehicle of Claim 13, wherein the motor controller is further configured to calculate the alpha and beta error voltages using a Clarke transformation.

21. The electric vehicle of Claim 13, wherein the motor controller is further configured to compensate for the alpha and beta error voltages by adding the alpha and beta error voltages to average alpha and beta voltages over a switching period of the PWM scheme.

Description:
DEAD TIME COMPENSATION USING AN ERROR VOLTAGE CALCULATION

INCORPORATION BY REFERENCE TO ANY PRIORITY APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 62/541,625, filed August 4, 2017, entitled "DEAD TIME COMPENSATION USING AN ERROR VOLTAGE CALCULATION," which is hereby incorporated by reference in its entirety and for all purposes.

FIELD

[0002] This disclosure relates generally to control of electric or electrical motors, and more particularly, to systems and methods for compensating dead time using an error voltage calculation.

BACKGROUND

[0003] Many vehicles and other systems are powered by electric motors using a voltage source such as a battery system or other energy storage device to provide electrical energy. Energy from the energy storage device may be provided to the motor as alternating current (AC) power by means of an inverter. For example, an inverter assembly may be configured to convert DC power from the energy storage device to AC power, and such AC power can be output to the motor.

SUMMARY

[0004] In one embodiment, a computer-implemented method for controlling an electric motor and compensating for errors introduced by dead time of a pulse width modulation (PWM) scheme is described. The method comprises calculating a first average voltage per a switching cycle of the PWM scheme, the first average voltage representing an ideal voltage of the switching cycle without the dead time; calculating a second average voltage per the switching cycle based on the first average voltage and the at least one correction term, the second average voltage representing an actual voltage of the switching cycle with the dead time; calculating an error voltage per the switching cycle based on the first and second average voltages, the error voltage representing a drop or increase in the voltage due of the switching cycle to the dead time in the switching cycle; generating a duty cycle command for driving the electric motor by compensating for the calculated error voltage; and driving the electric motor by selectively actuating, based on the calculated duty cycle command, a plurality of switches of an inverter electrically connected to the electric motor.

[0005] In some embodiments, the method further comprises determining a correction term based on one or more operating conditions of one or both of the electric motor and inverter and using the correction term to compensate for the calculated error voltage. In some embodiments, the method further comprises determining the at least one correction term as a function of a magnitude of a complex current vector. In some embodiments, the method further comprises determining whether to use a fade-in multiplier or a fade-out multiplier for the at least one correction term. In some embodiments, the method further comprises calculating the fade-in multiplier or fade-out multiplier over one fundamental period of the PWM scheme. In some embodiments, the method further comprises determining to use the fade-out multiplier and determining a value of the fade-out multiplier based on factors representing a percentage of a duty cycle not equal to 1 or 0 over one fundamental period. In some embodiments, the method further comprises calculating a phase error voltage for each phase of power to the electric motor, the phase error voltage computed based on the error voltage. In some embodiments, the method further comprises, for each phase of power, calculating the phase error voltage based on a phase voltage in a stationary frame. In some embodiments, the method further comprises, for each phase of power, multiplying the phase error voltage by a sign factor of a phase current of the phase of power, the sign factor of the phase current being equal to 1 if the phase current is greater than zero and equal to -1 if the phase current is less than zero. In some embodiments, the method further comprises, for each phase of power, converting the phase error voltage to alpha and beta voltage commands using a Clarke Transformation. In some embodiments, the method further comprises generating the duty cycle command for the inverter by at least, for each phase of power, using the alpha and beta error voltages to compensate original alpha and beta voltage commands. In some embodiments, the method further comprises calculating the error voltage per the switching cycle by calculating a difference between the first average voltage and the second average voltage.

[0006] In another embodiment, an electric vehicle is described. The electric vehicle comprises an AC electric motor; an energy storage device configured to supply DC power; an inverter configured to implement a pulse width modulation (PWM) scheme to convert the DC power into AC power for the AC electric motor, the inverter having a phase leg for each phase of the AC power, each phase leg comprising two switches electrically connected in series across the energy storage device, each phase leg electrically connected to one of the poles of the stator at a connection point between the two switches; and a motor controller comprising processing circuitry configured to selectively control each switch of the inverter between on and off positions to drive the motor by at least calculating an error voltage for each phase leg corresponding to a loss of average voltage due to dead time over a switching period of the PWM scheme, calculating alpha and beta error voltages corresponding to the calculated error voltages, generating a duty cycle command for the inverter by compensating for the alpha and beta error voltages, and driving the motor by selectively actuating the switches of the inverter based on the duty cycle command.

[0007] In some embodiments, the motor controller is further configured to multiply the alpha and beta error voltages by a correction term when generating the duty cycle command. In some embodiments, the motor controller is further configured to calculate the correction term as a fade-in multiplier that reduces the alpha and beta error voltage contributions to the duty cycle command at low phase currents. In some embodiments, the motor controller is further configured to calculate the fade-in multiplier as equal to a phase current magnitude divided by a predetermined threshold current when the phase current magnitude is less than the predetermined threshold current, and the fade-in multiplier is equal to 1 when the phase current magnitude is greater than or equal to the predetermined threshold current. In some embodiments, the motor controller is further configured to calculate the correction term as a fade-out multiplier that reduces the alpha and beta error voltage contributions to the duty cycle command at high modulation indices. In some embodiments, the motor controller is further configured to calculate the fade-out multiplier as equal to a percentage of a fundamental cycle in which the duty cycle is not equal to 0 or 1. In some embodiments, the motor controller is further configured to calculate the correction term as a multiplicative product of a fade-in multiplier and a fade-out multiplier, wherein the fade-in multiplier reduces the alpha and beta error voltage contributions to the duty cycle command at low phase currents, and wherein the fade-out multiplier reduces the alpha and beta error voltage contributions to the duty cycle command at high modulation indices. In some embodiments, the motor controller is further configured to calculate the alpha and beta error voltages using a Clarke transformation. In some embodiments, the motor controller is further configured to compensate for the alpha and beta error voltages by adding the alpha and beta error voltages to average alpha and beta voltages over a switching period of the PWM scheme.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a block diagram of an example embodiment of a vehicle equipped with an electric motor propulsion system.

[0009] FIG. 2 is a circuit diagram illustrating an example portion of a power inverter including a phase leg in accordance with an example embodiment.

[0010] FIGS. 3 A and 3B are diagrams illustrating example effects of dead time on pole voltage, according to an embodiment of the present disclosure.

[0011] FIG. 4 is a diagram illustrating example effects of dead time on a voltage fundamental, according to an embodiment of the present disclosure.

[0012] FIG. 5 is a diagram illustrating an exemplary relationship between a dead time compensation scaling factor and a modulation index, according to an embodiment of the present disclosure.

[0013] FIG. 6 is a flowchart illustrating an example method of dead time compensation.

[0014] FIG. 7 is a diagram that illustrates example experimental results of dead time compensation, according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0015] Generally described, the present disclosure relates to technology for compensating for error voltage introduced in electric systems. For example, in electric vehicles, the DC-AC inverter may implement a pulse-width modulation ("PWM") scheme to convert the DC power into AC power. PWM schemes can involve controlling the average value of voltage (and current) fed to a load by rapidly turning a switch between the supply and the load on and off. Generally, the longer the switch is on compared to the off periods, the higher the power supplied to the load. Typically, the PWM switching frequency is much higher than what would affect the load, such that the resultant waveform perceived by the load is as smooth as possible. In some implementations of pulse width modulation control schemes in voltage-fed inverters, a time delay while both switches of an inverter phase leg are open, also known as dead time, may be used to prevent a shoot through from the positive to the negative rail of a DC bus. Depending on the direction of the load current this dead time can lead to a gain or loss of voltage during a switching cycle. While avoiding shoot through can be advantageous, dead time may cause undesirable gain or loss of fundamental voltage or other output waveform distortion, referred to as the error voltage.

[0016] The aforementioned problems, among others, are addressed in some embodiments by the disclosed dead time compensation ("DTC") techniques that can prevent voltage loss due to the dead time. The DTC techniques can predict the error voltage introduced by the dead time, and can dynamically compensate for this predicted error voltage based on level of current. For example, the DTC techniques can disable compensation at zero current and increase the amount of compensation (for example, linearly) to the full dead time compensation at some predetermined current value. Compensation can include adding or subtracting the duty cycle lost or gained due to dead time insertion, or adding voltage lost due to dead time insertion back to the voltage command, in some implementations.

[0017] As would be appreciated by one of skill in the art, the use of dynamic dead time compensation, as disclosed herein, represents a significant technological advance over prior implementations. Specifically, the error voltage between the inverter output and the voltage that is commanded by the motor controller may be eliminated or mitigated, yielding more accurate motor control. In turn, this can lead to improved performance of the vehicle powered by the motor. As such, the embodiments described herein represent significant improvements in computer-related technology.

[0018] As will be appreciated, the fundamental voltage described herein is the voltage waveform produced by the supplied AC waveform, with the AC waveform cycling at the fundamental frequency. The term duty cycle describes the proportion of "on" time to the switching period, and is expressed in percent with 100% (or 1) being fully on. The switching period is the duration of time of one cycle of the repetitive switching, for example computed as the inverse of the frequency of the PWM scheme.

[0019] Various aspects of the disclosure will now be described with regard to certain examples and embodiments, which are intended to illustrate but not limit the disclosure. Although the examples and embodiments described herein will focus, for the purpose of illustration, specific calculations and algorithms, one of skill in the art will appreciate the examples are illustrate only, and are not intended to be limiting. For example, although described in the context of an electric vehicle, the disclosed DTC techniques can be implemented in other electric systems implementing PWM. Further, though described in the example context of a PWM scheme for an AC -DC inverter, the disclosed DTC techniques can be used in other electrical systems implementing PWM, for example for motor speed control.

Overview of Example PTC Systems and Techniques

[0020] FIG. 1 is a block diagram of an exemplary embodiment of a vehicle 100, according to one aspect of the disclosure. As shown in FIG. 1, vehicle 100 may include a chassis 110 and a plurality of wheels 112. Chassis 110 may be mechanically coupled to wheels 112 by, for example, a suspension system. Vehicle 100 may also include an electric or electrical motor propulsion system. For example, vehicle 100 may include one or more electric motors, such as motor 150, to supply motive torque. Wheels 112 may be coupled to motor 150 in various ways. In one embodiment, as illustrated in FIG. 1, opposite wheels may be connected through a shaft 114, which may be mechanically coupled to motor 150 to transmit torque and rotation from motor 150 to the wheels 112. In another embodiment, motor 150 may drive individual wheels directly, as illustrated, in a simplified manner, by a dashed line from motor 150 to the lower right wheel. For example, motor 150 may be located close to a wheel to provide driving power directly to the wheel. In this case, multiple motors may be used and each wheel may be driven by a separate motor or a group of motors. In another example, motor 150 may be built into a wheel such that the wheel may rotate co- axially with a rotor of the motor 150. Though depicted schematically as a car, the vehicle 100 can be any road or rail vehicle, aerial vehicle, boat or other water vehicle, or motive consumer electronic device, and the wheels 112 and shaft 114 (among other mechanical components) can be modified accordingly.

[0021] Motor 150 may be an AC synchronous electric motor including a rotor and a stator (not shown). The stator may include a plurality of poles, with each pole including windings connected to an AC power source, such as a three-phase AC power source. The rotor can be rotatably mounted concentrically within the stator, and the magnetically permeable rotor material is used to conduct magnetic flux. During operation, the AC powered stator may generate a rotating magnetic field (in the frame of reference of the stator) to drive the rotor to rotate. The rotor may include windings and/or permanent magnet(s) to form a number of magnetic poles such that a north/south pole of the magnet is continuously attracted by a south/north pole of the rotating magnetic field generated by the stator, thereby rotating synchronously with the rotating magnetic field. Exemplary AC synchronous electric motors include interior permanent magnet (IPM) motors, reluctance motors, and hysteresis motors. In some embodiments, the control system and method disclosed herein may also be used to control other types of motors.

[0022] Motor 150 may be controlled by a motor control system 140. Motor control system 140 may regulate energy transfer from an energy storage device 130 to motor 150 to drive motor 150. In some embodiments, motor 150 may operate in a generator mode, such as when vehicle 100 undergoes speed reduction or braking actions. In the generator mode, the excess motion energy may be used to drive motor 150 to generate electrical energy and feed the energy back to energy storage device 130 through motor control system 140. In some embodiments, energy storage device 130 may include one or more batteries to supply DC power. Motor control system 140 may include a DC- AC inverter to convert the DC power supplied by energy storage device 130 into AC driving power to drive motor 150. For example, the DC-AC inverter may include power electronic devices operating under a pulse- width modulation (PWM) scheme to convert the DC power into AC power. The motor control system 140 can further include a computing system (e.g., one or more hardware processors and one or more computer storage devices) configured to implement the disclosed DTC techniques.

[0023] Vehicle 100 may include a vehicle control module 120 to provide overall control of vehicle 100. For example, vehicle control module 120 may act as an interface between user operation and propulsion system reaction. For example, when a driver depresses an acceleration pedal of vehicle 100, vehicle control module 120 may translate the acceleration operation into a torque value to be output by motor 150, a target rotation speed of motor 150, or other similar parameters to be executed by the propulsion system. Vehicle control module 120 may be communicatively connected to motor control system 140 to supply commands and/or receive feedback. Vehicle control module 120 may also be communicatively connected to energy storage device to monitor operation status such as energy level, temperature, recharge count, etc.

[0024] A sensor 152 may detect the position of the rotor of motor 150. For example, sensor 152 may be a resolver assembly including a resolver stator and a resolver rotor. The resolver rotor may be affixed to the motor rotor concentrically or coaxially such that both the resolver rotor and the motor rotor rotate synchronously. The resolver rotor may include a plurality of lobes having eccentricities such that, when rotating, the position of the resolver rotor may be determined by detecting the proximity of the lobed resolver rotor to the resolver stator. The position of the motor rotor may then be determined based on the position of the resolver rotor. Motor control system 140 may receive the positional information as feedback data to determine the proper power application scheme (e.g., PWM switching timing).

[0025] FIG. 2 is a circuit diagram depicting a portion of an inverter which may be, for example, a portion of the motor control system 140 depicted in FIG. 1. The portion of the inverter depicted in FIG. 2 includes a single phase leg 200, or inverter leg, connected between a positive rail 202 and a negative rail 204 electrically coupled to positive and negative terminals of the energy storage device 130. The phase leg 200 includes a first switch 210 and a second switch 220. Switches 210 and 220 may be any type of switch. In the non-limiting example of FIG. 2, the first switch 210 includes a relay 212 such as a field effect transistor (e.g., a MOSFET), insulated-gate bipolar transistor (IGBT), or other solid state relay selectively permitting current to flow from a source 214 to a drain 216, and an anti-parallel diode 218. The second switch 220 similarly includes a relay 222 such as a field effect transistor (e.g., a MOSFET), insulated-gate bipolar transistor (IGBT), or other solid state relay selectively permitting current to flow from a source 224 to a drain 226, and an anti-parallel diode 228. The phase leg 200 is electrically connected to a load, such as a pole of the motor 150, at connection point A. In a vehicle powered by a three-phase motor 150, the inverter may include three phase legs 200, each of the three phase legs 200 including a connection point A coupled to a different pole of the motor 150 between switches.

[0026] Switches 210 and 220 may be independently switched in order to provide an AC current to the pole connected to the phase leg 200 at connection point A. Thus, while relay 212 is on and relay 222 is off, current can flow from the positive rail 202, through relay 212 from source 214 to drain 216, and to the load through connection point A (a "positive" current / ' ). While relay 212 is off and relay 222 is on, current can flow from the load through connection point A (a "negative" current / ' ), and to the negative rail 204 through relay 222 from source 224 to drain 216. Selective switching of relays 212 and 222 may be used to approximate an AC current, for example, through PWM such that the current i to the load is sinusoidal or approximately sinusoidal.

[0027] It will be appreciated that relays 212 and 222 should not be on at the same time, as this condition would create a low-resistance conductive path between the positive rail 202 and the negative rail 204. MOSFETs or other physical relays generally do not behave as ideal switches, and typically require a switching time to transition between fully on and fully off states. Although the switching time is generally short, the switching time may still be long enough that, if relays 212 and 222 are switched simultaneously, a conductive path may temporarily exist from the positive rail 202 to the negative rail 204, allowing for undesirable shoot through. Accordingly, in some implementations of PWM in voltage-fed inverters, a delay time may be inserted to prevent shoot through from the positive to the negative rail of the DC bus. This delay time may be a predetermined time interval greater than or equal to a switching time of relays 212 and 222, referred to herein as dead time. For example, if relay 212 is on and relay 222 is off, the motor control system 140 may switch relay 212 off, wait for the dead time to elapse, and switch relay 222 on after the dead time has elapsed. Accordingly, inclusion of a dead time in an inverter switching operation avoids shoot through by ensuring that a previously-on relay in each phase leg 200 is fully off before the other relay in the phase leg 200 is switched on.

[0028] As shown in FIGS. 3A and 3B, this dead time can lead to a gain or loss of voltage during a switching period or switching cycle, depending on the direction of the load current i. For a positive load current i > 0, as shown in FIG. 3 A, anti-parallel diode 228 pulls down the pole voltage during the inserted dead time 305a until relay 212 is turned on, which results in a voltage loss 310a during the switching cycle. For a negative load current i < 0, as shown in FIG. 3B, anti -parallel diode 218 pulls up the pole voltage during the inserted dead time 305b until relay 222 is turned on, which results in a voltage gain 310b during this switching cycle.

[0029] Further, contingent upon the sign of the fundamental voltage this can lead to the gain or loss of fundamental voltage. This is illustrated in the graph 400 of FIG. 4. The graph 400 depicts waveforms corresponding to current (i P h), fundamental voltage Vref), and dead time voltage (VDeadTime), as depicted by the legend 410. If the phase difference between voltage and current is smaller than 90° the insertion of dead time will typically lead to a loss of fundamental voltage. As will be appreciated, the fundamental voltage is the voltage waveform produced by the supplied AC waveform, with the AC waveform cycling at the fundamental frequency.

[0030] However, there are four general cases to consider, illustrated on the graph 400 by the circled numbers corresponding to the cases defined below:

(1) Case 1 (i<0 & v>0): Gain of fundamental voltage;

(2) Case 2 (i>0 & v>0): Loss of fundamental voltage;

(3) Case 3 (i>0 & v<0): Gain of fundamental voltage; and

(4) Case 4 (i<0 & v<0): Loss of fundamental voltage. Thus, when current and voltage are both either positive or negative, the insertion of dead time results in a loss of fundamental voltage. When current and voltage have opposite signs, the insertion of dead time results in a gain of fundamental voltage.

[0031] To prevent a voltage loss due to dead time, the disclosed compensation algorithm can be implemented. The details of particular implementations of the disclosed compensation algorithms may depend on the particular implementation of the PWM scheme. In some embodiments, a DTC method includes adding or subtracting the duty cycle that is lost or gained due to dead time insertion. However, in some cases this method may not fully compensate for all voltage losses over a switching cycle (e.g., voltage drop across the switching devices may not be addressed).

[0032] In some embodiments, another feasible approach is to add the voltage that is lost due to the dead time insertion back to the voltage command. The voltage lost due to the dead time insertion may be referred to as an "error voltage." As described herein, the disclosed voltage compensation may be dynamically scaled according to current operating conditions. FIG. 5 depicts a graph 500 illustrating an exemplary relationship between a dead time compensation scaling factor ("DTC multiplier", y-axis) and a modulation index (x-axis), according to an embodiment of the present disclosure. The graph 500 illustrates example values of the DTC multiplier in three different modes, with a space vector pulse width modulation (SVPWM) linear operation mode implemented for modulation indices less than 0.907, mode I implemented for modulation index values between 0.907 and 0.95, and mode II implemented for modulation index values between 0.95 and 1. In some embodiments, the modulation index may be defined as (V P hase)/((2/n)Vdc), where Vphase is a motor phase voltage, and Vdc is the DC bus voltage. As shown in the graph 500, the fade-out multiplier may generally decrease linearly in the mode I range, while in mode II the fade-out multiplier may decrease non-linearly to approach zero as the modulation index approaches 1.

[0033] Exemplary methods of adding the error voltage back to the alpha/beta voltage command in the stationary reference frame will now be described with reference to FIG. 6. Although the methods below are described with reference to phases or poles of a three-phase electric motor, it will be appreciated that the DTC methods described herein may equally be applied to various other types of electrical machines and other power electronics applications without departing from the scope of the present disclosure. [0034] FIG. 6 is a flowchart an example method 600 for controlling an electric motor. The method 600 can be implemented by the motor control system 140 in some implementations.

[0035] At block 602, the motor control system 140 can calculate a first average voltage per switching period before any dead time is inserted.

[0036] For example, in one implementation of block 602, an average voltage per switching period T s can be calculated for a pole or other load, both assuming no dead time is inserted (yielding a no dead time average voltage) and assuming dead time is inserted (yielding a dead time average voltage).

[0037] At block 604, the motor control system 140 can calculate an error voltage and at least one correction term based on one or more operating conditions. For example, in one implementation of block 604, the difference between the dead time average voltage and the no dead time average voltage yields the error voltage for that pole due to dead time insertion. The error voltage can represent the increase or drop in voltage due to the dead time. The voltages and currents are defined as shown in FIG. 2. The correction term can be computed, for example, as described with respect to FIG. 5 for high modulation indices, and/or as described elsewhere herein for low currents.

[0038] At block 606, the motor control system 140 can calculate a second average voltage per the switching period based on the first average voltage and the at least one correction term. For example, in one implementation if dead time is inserted, the average voltage per switching period YAO.DT (e.g., the average voltage of the switching period with dead time inserted) can be calculated as follows:

Vdc

= — (T s + 2 DT — 2 DC)

2 T S v s - J

[0039] In equation (la) above, DC is the switch-on time per duty cycle, DT is the inserted dead time, T s is the switching period, Vdc is the DC bus voltage as shown in FIG. 2, and VAo (t) is the pole voltage for phase A. Accordingly, DC/T S is the duty cycle. The voltage drop across the switches and the turn on/off time of the relays can be ignored in this implementation. If the turn on time Ton, and turn off time Jo are considered, the equation for the dead time average voltage can be calculated as follows:

[0040] As a next step, the device voltage drop across the switches can be considered as well. This can further improve the accuracy of the error voltage. However, the device drops have a much smaller impact on the error voltage than the dead time or the on/off times and can optionally be neglected.

[0041] In the ideal case with no dead time inserted the average voltage per switching period for a pole (e.g., the no dead time average voltage) can be calculated as follows:

[0042] As stated above, the error voltage introduced by the dead time insertion can be calculated by subtracting the average voltage per duty cycle with dead time inserted (the dead time average voltage) from the ideal case (the no dead time average voltage). In some implementations, this can be accomplished by subtracting equation (la) from equation (2):

DT (3)

V AO, err ~ ^AO ~ ¾0,DT ~ ± ~^~ V dc V )

[0043] At block 608, the motor control system 140 can calculate a phase error voltage for each phase. In some implementations, this phase error voltage calculation can be the same for each pole or phase {a,b,c} :

DT

V{AO,BO,CO},err ~ ± ~^~ Vdc (4)

* s [0044] The error term ( T S ) m equations (3) and (4) represents the error voltage, and is positive if the phase current is positive and negative if the phase current is negative. Since the controller uses the stationary α/β-voltages to calculate the duty cycles, the compensation may also be performed in the α/β-frame. Accordingly, at block 610, the motor control system 140 can convert the phase error voltages to duty cycles and the dead time can be applied. Specifically, in some implementations the abc-error terms can be transformed into the α/β-frame by an alpha-beta or Clarke transformation to determine v a ,err and v#err (the converted error voltage values):

^a.err ^ (^ ^ AO, err V BO, err ^CO.err ^} (5)

V β F ,err Vco,, (6)

[0045] In order to apply the dead time compensation, the voltage in the α/β-frame can be considered as:

Vet ^α,ηο DTC ^a.err

νβ = ν β,ηο DTC + v fi,err (g)

[0046] In equations (7) and (8) above, v a and νβ are the compensated voltages in the α/β-frame, v a ,ao DTC and v#no DTC are the uncompensated voltages, and v a ,err and νβ,εη- are the voltage compensation amounts determined by equations (5) and (6), respectively.

[0047] There are a few more implementation details that may be considered to further improve the dead time compensation methods described herein. First, dead time compensation at currents close to zero may not be required and might actually lead to erroneous results. Therefore, in some embodiments, the dead time compensation may be disabled at zero current and may be linearly increased to the full dead time compensation at some specific current such as a predetermined threshold current. Above the predetermined threshold current, the full error voltage can be applied. In one particular example, the predetermined threshold current can be set to IDTO = 10 A, although other predetermined threshold values are possible. This function can be implemented using a low-current or fade- in multiplier KLC that is a function of the magnitude of the complex current vector . In the context of this application, the terms "multiplier" and "correction term" can be used interchangeably. In other words, a multiplier can be a correction term. An example fade-in multiplier KLC may be defined as:

[0048] A second implementation detail concerns operation at high modulation indices. The maximum fundamental voltage that can be generated by the inverter is (2/ )Vdc, which is reached for a modulation index of one (e.g., six-step operation). For this operating point, the duty cycle for each phase is either one or zero and no dead time is inserted since the switch is either on or off for the entire switching period. Since no dead time is inserted, no dead time compensation is needed. If the dead time compensation algorithm still adds the full error voltage, this can lead to an undesired voltage boost. Accordingly, an error voltage reduction may be employed in the form of an overmodulation or fade-out multiplier KOM to avoid this undesired voltage boost. Hence, the error voltage reduction may start at this point.

[0049] At a modulation index of 0.85, for example, the fade-out multiplier KOM may be equal to one and may be decreased to zero when six-step operation is reached (e.g., at a modulation index of 1). In between those two points, the multiplier can be determined based on the percentage of duty cycles where one or zero are applied during a fundamental cycle. For example, in some embodiments, for a modulation index of 0.98 a duty cycle of one or zero is applied during -80% of the fundamental cycle. Thus, the error voltage can be multiplied by (1-0.8), or 0.2, to get the appropriate dead time compensation voltage. The function is non-linear and in some embodiments may be pre-calculated and stored in a lookup table. An example relationship between the fade-out multiplier and the modulation index is shown in FIG. 5.

[0050] The fade-in and fade-out multipliers can thus be included in the alpha-beta voltages represented in equations (7) and (8) as follows: a, no DTC + K 0M K LC v a err (10) νβ — ν β,ηο DTC + KOM KLC ν β, , ι err (11) [0051] One benefit yielded by the disclosed dead time compensation is that the error voltage between the inverter output and the voltage that is commanded by the motor controller may be eliminated or mitigated, e.g., the commanded and applied modulation index should match. An experimental result for a set of example operating points is shown in FIG. 7. The graph 700 of FIG. 7 plots modulation index (y-axis) across a number of test points (x-axis). In the graph 700, a commanded modulation index is depicted in a solid line. First and second tests are depicted in different dotted line types, as depicted in the legend 710. If no dead time compensation is applied (Test #1, small dotted line) there is a clear mismatch between the commanded (Cmd, solid line) and applied voltage. This mismatch is substantially eliminated by the dead time compensation algorithm described herein (Test #2, large dotted line).

Terminology

[0052] All of the methods and tasks described herein may be performed and fully automated by a computer system. The computer system typically includes a processor (or multiple processors) that executes program instructions or modules stored in a memory or other non-transitory computer-readable storage medium or device (e.g., solid state storage devices hard drive, flash memory, removable media, etc.). A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of a non-transitory computer-readable storage medium. The various functions disclosed herein may be embodied in such program instructions, or may be implemented in application-specific circuitry (e.g., ASICs or FPGAs) of the computer system. The results of the disclosed methods and tasks may be persistently stored by transforming physical storage devices, such as solid-state memory chips or magnetic disks, into a different state. An exemplary storage medium can be coupled to the processor device such that the processor device can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor device.

[0053] The disclosed processes may begin in response to an event, such as on a predetermined or dynamically determined schedule, or in response to some other event. When the process is initiated, a set of executable program instructions stored on one or more non-transitory computer-readable media may be loaded into memory (e.g., RAM) of a computing device. The executable instructions may then be executed by a hardware-based computer processor of the computing device. A processor device can be a microprocessor, but in the alternative, the processor device can be a controller, microcontroller, or state machine, combinations of the same, or the like. A processor device can include electrical circuitry configured to process computer-executable instructions. In another embodiment, a processor device includes an FPGA or other programmable device that performs logic operations without processing computer-executable instructions. A processor device can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0054] In some embodiments, the process or portions thereof may be implemented on multiple computing devices and/or multiple processors, serially or in parallel. Depending on the embodiment, certain acts, events, or functions of any of the processes or algorithms described herein can be performed in a different sequence, can be added, merged, or left out altogether (e.g., not all described operations or events are necessary for the practice of the algorithm). Moreover, in certain embodiments, operations or events can be performed concurrently, e.g., through multi-threaded processing, interrupt processing, or multiple processors or processor cores or on other parallel architectures, rather than sequentially.

[0055] The various illustrative logical blocks, modules, and process steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. The described functionality can be implemented in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure.

[0056] While examples and features of disclosed embodiments are described herein, modifications, adaptations, and other implementations are possible without departing from the spirit and scope of the disclosed embodiments. Also, the words "comprising," "having," "containing," and "including," and other similar forms are intended to be equivalent in meaning and be open ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items. It must also be noted that as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise.

[0057] Conditional language used herein, such as, among others, "can," "might," "may," "e.g.," and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without author input or prompting, whether these features, elements and/or states are included or are to be performed in any particular embodiment.

[0058] While the above detailed description has shown, described, and pointed out novel features as applied to illustrative embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the devices or processes illustrated can be made without departing from the scope of the disclosure. As will be recognized, certain embodiments described herein can be embodied within a form that does not provide all of the features and benefits set forth herein, as some features can be used or practiced separately from others. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.