Title:
DEAD TIME GENERATOR AND DIGITAL SIGNAL PROCESSING DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/021709
Kind Code:
A1
Abstract:
A clock synchronization signal generator (40) generates a dead time at which both gates of two switching elements included in a switching circuit (52) go into an off state, and generates the dead time for controlling a plurality of pulses with different widths to pulses with a constant width to be outputted by the switching circuit (52).
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Inventors:
NAKAHIRA TSUYOSHI
NISHIGAKI AKIHIRO
NISHIGAKI AKIHIRO
Application Number:
PCT/JP2018/023844
Publication Date:
January 31, 2019
Filing Date:
June 22, 2018
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
H03F3/217; H03F3/185; H03F3/68
Foreign References:
JP2007124574A | 2007-05-17 | |||
JP2000068841A | 2000-03-03 | |||
US20060208798A1 | 2006-09-21 |
Other References:
CHEN HSIN-CHUAN: "A Dead-Time Generator Based on OPA Slew Rate for Consumer Electronic Applications", 2014 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS- TAIWAN, 2014, Taiwan, pages 137 - 138, XP032646008, DOI: 10.1109/ICCE-TW.2014.6904024
Attorney, Agent or Firm:
HARAKENZO WORLD PATENT & TRADEMARK (JP)
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