Title:
DEBUGGER AND DEBUGGING METHOD
Document Type and Number:
WIPO Patent Application WO/2008/020513
Kind Code:
A1
Abstract:
A debugger comprises a break detecting circuit for generating a break request signal to request the transition of a microprocessor core to a debug state when the state of the microprocessor core matches a preset condition, a trigger detecting circuit for generating a trigger request signal to request the observation of a predetermined signal when the predetermined signal of additional hardware matches the preset condition, and an execution control circuit for outputting the trigger signal for observing the predetermined signal by means of a logic analyzer when the trigger request signal is generated and outputting the break signal for allowing the transition of the microprocessor core to the debug state.
Inventors:
NADEHARA, Kouhei (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 1088001, JP)
Application Number:
JP2007/063370
Publication Date:
February 21, 2008
Filing Date:
July 04, 2007
Export Citation:
Assignee:
NEC CORPORATION (7-1 Shiba 5-chome, Minato-ku Tokyo, 01, 1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 1088001, JP)
International Classes:
G06F11/28
Attorney, Agent or Firm:
MIYAZAKI, Teruo et al. (8th Floor, 16th Kowa Bldg. 9-20, Akasaka 1-chome Minato-k, Tokyo 52, 1070052, JP)