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Patent Searching and Data


Title:
DECISION FEEDBACK EQUALIZER AND RECEIVER USING SAME
Document Type and Number:
WIPO Patent Application WO/2019/167275
Kind Code:
A1
Abstract:
The purpose of the invention is to reduce bit errors caused by circuit linearity and data pattern. An aspect of the invention is a decision feedback equalizer comprising: a first adder that adds a correction value to an input signal; a decision unit that decides a logic value from an output of the first adder according to a first decision threshold value; a flip-flop that samples and holds an output of the decision unit at the timing of a clock; a shift register that receives an output of the flip-flop and the clock and delays the output of the flip-flop in each clock period; a multiplier that multiplies the output of the flip-flop and an output of the shift register by a correction coefficient and outputs a correction value; a correction coefficient calculator that calculates, from the output of the first adder and the output of the flip-flop, the correction coefficient at each timing of the clock; a decision threshold value calculator that calculates, from the output of the first adder and the output of the flip-flop, a second decision threshold value at each timing of the clock; and a second adder that adds a threshold value offset to the second decision threshold value and outputs the first decision threshold value.

Inventors:
NORIMATSU Takayasu (6-6, Marunouchi 1-chome, Chiyoda-k, Tokyo 80, 〒1008280, JP)
Application Number:
JP2018/008129
Publication Date:
September 06, 2019
Filing Date:
March 02, 2018
Export Citation:
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Assignee:
HITACHI, LTD. (6-6 Marunouchi 1-chome, Chiyoda-ku Tokyo, 80, 〒1008280, JP)
International Classes:
H04B3/06
Domestic Patent References:
WO2012102258A12012-08-02
Foreign References:
JP2017041825A2017-02-23
JP2015211270A2015-11-24
EP1545030A22005-06-22
US20050019042A12005-01-27
JP2004166231A2004-06-10
Attorney, Agent or Firm:
SEIRYO I.P.C. (24-2, Hatchobori 2-chome Chuo-k, Tokyo 32, 〒1040032, JP)
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