Title:
DECISION FEEDBACK EQUALIZER
Document Type and Number:
WIPO Patent Application WO/2012/102258
Kind Code:
A1
Abstract:
The objective of the present invention is operability at a higher speed. The present invention is provided with (FIG. 1): a weighted summing circuit (an adder (21) and coefficient multipliers (Tap 1a, Tap 2 to Tap n)) for adding an input signal and each of the respective signals which are weighted feedback signals (FB1 to FBn) (n is an integer greater than or equal to 2); a decision circuit (11), which operates in synchronization with a clock signal, for assessing whether or not the summed result of the weighted summing circuit is greater than or equal to a predetermined threshold in order to output the assessment result to the outside and to a shift register (latch circuits (L2 to Ln)); the shift register, which sequentially holds the assessment result of the decision circuit (11) in synchronization with the clock signal in order to output the held contents of each of the registers, which are constituent elements, as the feedback signals (FB2 to FBn); and a decision circuit (12), which operates in synchronization with the clock signal, for assessing whether or not the summed result of the weighted summing circuit is greater than or equal to a predetermined threshold in order to output the assessment result as the feedback signal (FB1).
Inventors:
AMAMIYA YASUSHI (JP)
Application Number:
PCT/JP2012/051409
Publication Date:
August 02, 2012
Filing Date:
January 24, 2012
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP (JP)
AMAMIYA YASUSHI (JP)
AMAMIYA YASUSHI (JP)
International Classes:
H03H17/00; H04B3/06
Domestic Patent References:
| WO2008041609A1 | 2008-04-10 |
Foreign References:
| JPH06204902A | 1994-07-22 | |||
| JPH08204624A | 1996-08-09 |
Other References:
ROBERT PAYNE ET AL.: "A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications", 2005 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 2005. DIGEST OF TECHNICAL PAPERS. ISSCC., vol. 1, 10 February 2005 (2005-02-10), pages 68,69,585
BO WANG ET AL.: "A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel", CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, 2009. CCECE '09., 3 May 2009 (2009-05-03), pages 1221 - 1226, XP031477516
ADESH GARG ET AL.: "A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-um SiGe BiCMOS Technology", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 41, no. 10, October 2006 (2006-10-01), pages 2224 - 2232
SRINIVASA R.SRIDHARA ET AL.: "Joint Equalization and Coding for On-Chip Bus Communication", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 16, no. 3, March 2008 (2008-03-01), pages 314 - 318
BO WANG ET AL.: "A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel", CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, 2009. CCECE '09., 3 May 2009 (2009-05-03), pages 1221 - 1226, XP031477516
ADESH GARG ET AL.: "A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-um SiGe BiCMOS Technology", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 41, no. 10, October 2006 (2006-10-01), pages 2224 - 2232
SRINIVASA R.SRIDHARA ET AL.: "Joint Equalization and Coding for On-Chip Bus Communication", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 16, no. 3, March 2008 (2008-03-01), pages 314 - 318
Attorney, Agent or Firm:
KATO, Asamichi (JP)
Asamichi Kato (JP)
Asamichi Kato (JP)
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Claims: