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Patent Searching and Data


Title:
DECODING CIRCUIT AND CHIP
Document Type and Number:
WIPO Patent Application WO/2021/209067
Kind Code:
A1
Abstract:
The present invention provides a decoding circuit and chip; said decoding circuit comprises a charging and discharging unit, a capacitor, and a conversion unit, connected in sequence; said charging and discharging unit is configured to: charge and discharge the capacitor, and the ratio of the total time consumed for charging the capacitor with any amount of power to the total time consumed for releasing the same amount of power on the capacitor is a preset value; the conversion unit is configured to: if the voltage of the capacitor exceeds a preset voltage, output a third level, otherwise, output a fourth level. Such a configuration reduces the calculation burden of an MCU; eliminates the influence of noise on a communication signal, and increases the effective communication distance of the HBS protocol; it adapts to communication signals of different clock cycles. The invention solves the problems in the prior art of a relatively heavy computational burden of an MCU, there being a contradiction between error correction and communication distance, and poor adaptability to communication signals of different clock cycles.

Inventors:
LI RUIPING (CN)
CHI WEI (CN)
LIU BIN (CN)
WANG JIANHU (CN)
Application Number:
PCT/CN2021/088126
Publication Date:
October 21, 2021
Filing Date:
April 19, 2021
Export Citation:
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Assignee:
SHANGHAI XINLONG SEMICONDUCTOR TECH CO LTD (CN)
International Classes:
H04B14/02
Foreign References:
CN112039606A2020-12-04
CN104283569A2015-01-14
CN110266339A2019-09-20
CN210327616U2020-04-14
US20040141560A12004-07-22
Attorney, Agent or Firm:
SHANGHAI SAVVY IP AGENCY CO., LTD. (CN)
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