Decoding logic for generating a n-bit binary output signal on the basis of an intermediate n- bit Gray signal The invention relates to a decoding logic for generating a n-bit binary output signal on the basis of an intermediate n-bit Gray signal, comprising a first series connection of respective logic units of a first kind for generating respective bits of the n-bit binary output signal, wherein the nth bits of the respective signals are the most significant bits and wherein the 1th bits of the respective signals are the least significant bits of the respective signals, and wherein, in use, the mth logic unit of the first kind, wherein m= 1,..., (n-1), generates the (n- m) th bit of the n-bit binary output signal on the basis of the (n-m+1) th bit of the binary output signal and the (n-m) th bit of the Gray signal.

Decoding logics of this kind are known in practice and are used in flash A/D converters. In these flash A/D converters, in a first step, a thermometer signal is generated on the basis of signals originating from an array of comparators. Subsequently, in a second step, an intermediate Gray signal is generated on the basis of the thermometer signal. Then, in a third step, a binary output signal is generated on the basis of the intermediate Gray signal.

The second step is applied in order to reduce converting errors which can arise in a direct conversion from the thermometer signal to the binary output signal.

In the known decoding logic for generating the binary output signal the logic units of the first kind are exclusive-or (EXOR) -gates. Although the mathematical formulation of the decoding logic in terms of EXOR-functions is the most simple formulation, a direct implementation of this formulation does not lead a topology for a fast operating decoding logic. This is a consequence of the fact that the known EXOR-gates are, due to their complexity, not very fast operating logical hardware components.

It is an object of the invention to provide a decoding logic with an efficient and relatively fast topology. For this, the required transformation from the Gray signal to the binary output signal is re-formulated in terms of mathematical functions which correspond with fast operating logical hardware components. This yields a decoding logic according to the invention which is characterised in that the mh logic unit of the first kind consists of one or more AND-gates, one or more NAND-gates and/or an OR-gate. In this way, the logic units of the first kind are only built op with fast gates, yielding a relatively fast decoding logic.

It is noted that the decoding logic according to the invention can also be provided with gates serving as delay-elements for timing purposes.

A first embodiment of the decoding logic according to the invention is characterised in that the mth logic unit of the first kind comprises a first NAND-gate, a second NAND-gate and a third NAND-gate, wherein the output of the first NAND-gate is connected with a first input of the third NAND-gate and wherein the output of the second NAND-gate is connected with a second input of the third NAND-gate, wherein, in use, the (n-m+l) th bit of the binary output signal is fed to a first input of the first NAND-gate and the inverted (n-m) th bit of the Gray signal is fed to a second input of the first NAND-gate, and wherein the inverted (n-m+1) t" bit of the binary output signal is fed to a first input of the second NAND- gate and the (n-m) th bit of the Gray signal is fed to a second input of the second NAND-gate, wherein the output of the third NAND-gate is the (n-m) h bit of the n-bit binary output signal.

The topology of the decoding logic wherein each logic unit of the first kind comprises three NAND-gates is functionally equivalent with the topology of the known decoding logic wherein each logic unit of the first kind comprises a known EXOR-gate. However, the topology of decoding logic according to the invention is matched with advantageous logic hardware components and thus can operate considerably faster than the known decoding logic.

A second embodiment according to the invention is characterised in that the mth logic unit of the first kind comprises a first AND-gate, a second AND-gate and an OR- gate, wherein the output of the first AND-gate is connected with a first input of the OR-gate and wherein the output of the second AND-gate is connected with a second input of the OR- gate, wherein, in use, the (n-m+l)'h bit of the binary output signal is fed to a first input of the first AND-gate and the inverted (n-m)'h bit of the Gray signal is fed to a second input of the first AND-gate, and wherein the inverted (n-m+1) th bit of the binary output signal is fed to a first input of the second AND-gate and the (n-m) th bit of the Gray signal is fed to a second input of the second AND-gate, wherein the output of the OR-gate is the (n-m) th bit of the n- bit binary output signal. The topology of the two AND-gates and the OR-gate in the logic units of the first kind is functionally equivalent with an EXOR-function, but the decoding logic according to the second embodiment can operate considerably faster than the known decoding logic which is provided with a known EXOR-gate.

Both in the first embodiment and the second embodiment the math logic unit of the first kind has to be fed with the (n-m+1) th inverted bit of the binary output signal (m=l,..., n-1). Herewith, the Ilh logic unit of the first kind can be fed with the inverted nth

inverted bit of the Gray signal since the nth bit of the n bit binary output signal is equal to the nth bit of the n bit Gray signal. The (n-p) th inverted bit (p=l,..., n-2) of the binary output signal can be generated in principle in two different ways.

A first way of generating the (n-p) Ih inverted bit (p=1,..., n-2) of the binary output signal is to connect an inverter between succeeding logic units of the first kind for generating the inverted bit of the binary output signal on the basis of the output of a preceding logic unit of the first kind. An advantage of the this is that it yields a relatively simple and cheap topology. A disadvantage is that the inverter is connected in series with the logic units of the first kind, such that it introduces an extra time delay.

According to a second way a relatively fast topology for the decoding logic according to the invention is achieved wherein the inverted (n-m+1) th bit of the binary output signal is calculated in parallel with the (n-m+1) th bit of the binary output signal. For this, an embodiment according to the invention is characterised in that the decoding logic also comprises a second series connection of respective logic units of a second kind, wherein the pth logic unit of the second kind, wherein p= 1,..., (n-2), comprises a first NOR-gate, a second NOR-gate and a third NOR-gate, wherein the output of the first NOR-gate is connected with a first input of the third NOR-gate and wherein the output of the second NOR-gate is connected with a second input of the third NOR-gate, and wherein the output of the third NOR-gate is connected with an input of the (p+1) th logic unit of the first kind, wherein, in use, the (n-p+1) th bit of the binary output signal is fed to a first input of the first NOR-gate and the inverted (n-p) h bit of the Gray signal is fed to a second input of the first NOR-gate, and wherein the inverted (n-p+1) th bit of the binary output signal is fed to a first input of the second NOR-gate and the (n-p) th bit of the Gray signal is fed to a second input of the second NOR-gate, wherein the output of the third NOR-gate is the inverted (n-p) th bit of the n-bit binary output signal which is fed to the (p+1) th logic unit of the first kind. In this embodiment the (n-m)'h bit of the binary output signal is calculated by the mh logic unit of the first kind while the inverted (n-p) th bit of the binary output signal is calculated in parallel by the (p=m) th logic unit of the second kind. Next, the outputs of the logic units of the first and second kind are fed to the inputs of the succeeding logic units of the first and second kind.

In the accompanying drawings in which certain modes for carrying out the present invention are shown for illustrative purposes:

Figure 1 is a schematic diagram of a decoding logic according to the invention for generating a n-bit binary output signal on the basis of an intermediate n-bit Gray signal; Figure 2A is a schematic diagram of a first embodiment of a logic unit of the first kind of the decoding logic of figure 1; Figure 2B is a schematic diagram of a second embodiment of a logic unit of the first kind of the decoding logic of figure 1; Figure 3 is a schematic diagram of a first embodiment of a logic unit of the second kind of the decoding logic of figure 1.

Figure 1 schematically shows a decoding logic 2 which can be used in a flash A/D converter for generating a n-bit binary output signal 4 on the basis of an (intermediate) n-bit Gray signal 6. The decoding logic 2 has a recursive structure and comprises a first series connection of respective logic units of a first kind 8. m, m=1,..., n-1 for generating the respective bits of the n-bit binary output signal 4.

Hereinafter, the following notation will be applied. The n bit binary output signal 4 is notated as (Bns Bn l,..., Bl), wherein the bit Bn is the most significant bit and Bl is the least significant bit. In an analogous way, the Gray signal 6 is notated as (Gn, Gn lX G,).

The (n-k)'h bit of the n-bit binary output signal is Bn-k and the inverted (n-k)'h bit of the n-bit binary output signal is notated as B n-k (k=0,..., n-1). Furthermore, the (n-k) th bit of the Gray signal is Gn-k and the inverted (n-k)'h bit of the Gray signal is notated as G n-k (k=0,..., n-1).

With the notation according to the preceding paragraph the transformation from the intermediate n bit Gray signal to the n-bit binary output signal can be written with the following (recursive) formulas (I) : wherein s is the mathematical exclusive-or function. A direct implementation of (I) would yield a relatively slow circuitry. This is a consequence of the fact that an EXOR-gate has a relatively complex topology as a consequence of which it is a relatively slow operating logical hardware component. In contrast, NAND-gates, AND-gates, OR-gates and NOR- gates have simple topologies and are fast operating logical hardware components. For achieving a relatively fast operating decoding logic 2 according to the invention, the equations (I) have to be re-formulated in terms of mathematical functions which can be

performed by relatively fast logical hardware components. This re-formulation according to the invention yields two possible sets of equations (II) and (III) and thus two advantageous topologies for the logic unit of the first kind.

The first set of equations (II) is: wherein is the logical mathematical AND function and wherein the bars over the mathematical entities are mathematical inversion functions.

The second set of equations (II) is: wherein + is the logical mathematical OR function. Later on, it will be explained how the respective sets of equations (II) and (III) relate to the respective first and second embodiments of logic units of the first kind.

The decoding logic 2 receives the Gray signal 6 (Gn, G"_1,..., Gl) for generating the n bit binary output signal (Bn, Bn l,..., Bl). From figure 1 it is clear that the logic units 8. m (m=1,..., n-1) of the first kind have to be fed both with the bits of the Gray signal 6 and with the inverted bits of the Gray signal. In principle, the decoding unit 2 can generate the inversed bits 10 of the Gray signal in a straightforward way by inverting the bits of the Gray signal 6. However, in this case the decoding logic 2 can be directly provided with these inverted bits (G", G"_1,..., G 1) 10 of the Gray signal 6 (see figure 1) since the decoding unit 2 is used in a configuration in which the inverted bits of the Gray signal 10 are already generated at the outputs of flip-flops of this configuration. Accordingly, logical inversion gates are saved such that unnecessary time delays are prevented which yields a faster decoding logic 2. The bits of the Gray signal 6 and the inverted bits 10 of the Gray signal can

be distributed via the connection 12 to the respective logic units of the first kind 8. m (m=1,..., n-l).

As shown in figure 1, the logic units of the first kind are part of a recursive first series connection. Figures 2A and 2B show that the mth logic unit of the first kind 8. m (m=l,..., n-1) can generate the bit Bn-m on the basis of bit Bn-m+i, the inverted bit B n-milz the bit Gn-m and the inverted bit G n-m. For the initialization of the logic unit 8.1 the equations Bn=Gn and B n= are used. The logic unit of the first kind 8.1 can generate the bit Bon l on the basis of the bits Gn, Gn l, G n and G n-l Hereinafter two possible topologies for the logic units of the first kind 8. m (m=l,..., n-1) according to the invention are discussed and described with reference to the figures 2A and 2B. For each of these logic units of the first kind a circuitry is applied which only comprises one or more NAND-gates, one or more AND-gates and/or an OR-gate. With these gates it is possible to realize a decoding logic which can operate considerably faster than the known logic unit which comprises a logical hardware component such as an EXOR- gate.

Figure 2A is a first embodiment of the mth logic unit 8. m of the first kind which is based on the set of equations (II), wherein m=l,..., n-1. The mth logic unit of the first kind comprises a first NAND-gate 14.1, a second NAND-gate 14.2 and a third NAND-gate 14.3. An output of the first NAND-gate 14.1 is connected with a first input of the third NAND-gate 14.3 and an output of the second NAND-gate 14.2 is connected with a second input of the third NAND-gate 14.3. The bit Bn-m+l is fed to a first input of the first NAND- gate 14.1 and the inverted bit n-n, is fed to a second input of the first NAND-gate 14.1.

Furthermore, the inverted bit B n-m+l is fed to a first input of the second NAND-gate 14.2 and the bit Gn-m is fed to a second input of the second NAND-gate 14.2. In this way a logic unit of the first kind 18. m is realized which generates the bit Bn-,,, at the output of the third NAND-gate 14.3.

Figure 2B is a second embodiment of the mth logic unit 8. m of the first kind which is based on the set of equations (III), wherein m=l,..., n-1. The mth logic unit 8. m of the first kind comprises a first AND-gate 16.1, a second AND-gate 16.2 and an OR-gate 18.

An output of the first AND-gate 16.1 is connected with a first input of the OR-gate 18 and an output of the second AND-gate 16.2 is connected with a second input of the OR-gate 18. The bit Bn-m+l is fed to a first input of the first AND-gate 16.1 and the inverted bit G n-m is fed to a second input of the first AND-gate 16. 1. Furthermore, the bit B n-m+l is fed to a first input

of the second AND-gate 16.2 and the bit Gon m is fed to a second input of the second AND- gate 16.2. Finally, the bit B is generated by the OR-gate 18.

It follows from the set of equations (1) that the bit Bn=Gn and that the inverted bit B n= G n such that the logic unit 8.1 can generate the bit Bon l solely on the basis of the bits Gn, Gn-i, G n, G n-l. In a way the logic unit 8.1 of the first kind initializes the (recursive) first series connection of logic units of the first kind.

In Figure 1 it is shown that the decoding logic 2 also comprises a second series connection of logic units of a second kind 20. p (p=l,..., n-2), wherein the logic units of the second kind can be provided with the bits of the Gray signal 6 and the inverted bits 10 of the Gray signal 6 via the connection 12. The logic unit 20. p of the second kind generates the inverted bit which can be used both by the succeeding logic unit of the first kind 8. (p+1) and the succeeding logic unit of the second kind 20. (p+1), (p=l,..., n-2). In figure 3 it is shown that the logic unit 20. p comprises a first NOR-gate 22.1, a second NOR-gate 22.2 and a third NOR-gate 22.3. The output of the first NOR-gate 22.1 is connected with a first input of the third NOR-gate 22.3 and the output of the second NOR-gate 22.2 is connected with a second input of the third NOR-gate 22.3. The first input of the first NOR-gate 22.1 can be fed with the bit G n-p and the second input of the first NOR-gate 22.1 can be fed with the bit Bn- p+z Furthermore, the bit n-p+i can be fed to a first input of the second NOR-gate 22.2 and the bit Gn-p can be fed to a second input of the second NOR-gate 22.2. Finally, the bit B n-p is generated by the third NOR-gate 22.3. The thus generated bit B n-p can be fed to the logic unit of the first kind 8. (p+1) and to the logic unit of the second kind 20. (p+1). The first series of logic units of the first kind 8. m are disposed in parallel with the second series of logic units of the second kind 20. p (m=l,..., n-1 ; p=l,..., n-1). Consequently, the bits Bn-m and. 8 n-p (wherein, in this case, m=p) can be generated in parallel such that a relatively fast decoding logic is realized for generating the n bit binary output signal 4 in a relatively short time.

The invention has been described according to a few embodiments. However, it should be noted that the invention can be practised with embodiments provided with modifications and variations otherwise than as specifically illustrated and described without departing from its spirit or scope. Such a modification is an embodiment of the decoding logic which comprises inverters instead of the second series, wherein the inverters are connected between succeeding logic units of the first kind for inverting the bits of the binary output signal. Another modification is an embodiment of the decoding logic which comprises functionally void logic units for timing purposes.