Title:
DECODING METHOD FOR MULTI-THREAD PROCESSOR, PROCESSOR, CHIP, AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/093541
Kind Code:
A1
Abstract:
Embodiments of the present disclosure provide a decoding method for a multi-thread processor, a processor, a chip, and an electronic device. The method comprises: fetching an instruction stream according to an instruction fetch request; splitting the fetched instruction stream in response to a multi-thread processor being in a single-threaded mode; using instructions at split positions as boundaries of switching instruction queues, and distributing the split instruction stream to a plurality of target instruction queues, wherein the plurality of target instruction queues comprise instruction queues corresponding to active threads and instruction queues corresponding to inactive threads; and decoding the instructions in the plurality of target instruction queues by using a plurality of decoder groups to obtain micro-ops obtained after decoding by the decoder groups. The embodiments of the present disclosure can improve the decoding efficiency of a multi-thread processor while being compatible with multiple thread modes.
Inventors:
CUI ZEHAN (CN)
Application Number:
PCT/CN2023/118573
Publication Date:
May 10, 2024
Filing Date:
September 13, 2023
Export Citation:
Assignee:
HYGON INFORMATION TECH CO LTD (CN)
International Classes:
G06F9/38
Foreign References:
| CN115629807A | 2023-01-20 | |||
| CN106406814A | 2017-02-15 | |||
| CN111679857A | 2020-09-18 | |||
| CN104572016A | 2015-04-29 | |||
| DE60035480D1 | 2007-08-23 | |||
| US20220100519A1 | 2022-03-31 | |||
| CN114090077A | 2022-02-25 |
Attorney, Agent or Firm:
LIU , SHEN & ASSOCIATES (CN)
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