Title:
DECOUPLING CAPACITORS FOR THIN GATE OXIDES
Document Type and Number:
WIPO Patent Application WO2001046989
Kind Code:
A3
Abstract:
In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.
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Inventors:
KESHAVARZI ALI (IR)
DE VIVEK K (IN)
KARNIK TANAY (IN)
NAIR RAJENDRAN (IN)
DE VIVEK K (IN)
KARNIK TANAY (IN)
NAIR RAJENDRAN (IN)
Application Number:
PCT/US2000/031352
Publication Date:
May 10, 2002
Filing Date:
November 13, 2000
Export Citation:
Assignee:
INTEL CORP (US)
KESHAVARZI ALI (IR)
VIVEK K DE (IN)
KARNIK TANAY (IN)
NAIR RAJENDRAN (IN)
KESHAVARZI ALI (IR)
VIVEK K DE (IN)
KARNIK TANAY (IN)
NAIR RAJENDRAN (IN)
International Classes:
H01L27/04; H01L21/822; H01L27/08; H01L29/94; (IPC1-7): H01L29/94; H01L27/06
Foreign References:
| US5032892A | 1991-07-16 | |||
| US5962887A | 1999-10-05 |
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