Title:
DECOUPLING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2013/073591
Kind Code:
A1
Abstract:
This decoupling circuit is provided with: an output buffer, which includes a transistor; and a capacitor, which has one end thereof connected to an output node of the output buffer, and has the other end thereof connected to a power supply line. A logic level which the output node of the output buffer outputs is fixed.
Inventors:
KASHIWAKURA KAZUHIRO (JP)
Application Number:
PCT/JP2012/079545
Publication Date:
May 23, 2013
Filing Date:
November 14, 2012
Export Citation:
Assignee:
NEC CORP (JP)
KASHIWAKURA KAZUHIRO (JP)
KASHIWAKURA KAZUHIRO (JP)
International Classes:
H01L21/822; H01L27/04
Foreign References:
| JP2006032823A | 2006-02-02 | |||
| JP2003086699A | 2003-03-20 | |||
| JP2011124615A | 2011-06-23 | |||
| JP2008520109A | 2008-06-12 | |||
| JP2006304346A | 2006-11-02 |
Attorney, Agent or Firm:
KATO, Asamichi (JP)
Asamichi Kato (JP)
Asamichi Kato (JP)
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Claims: