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Title:
DEEP N WELLS IN TRIPLE WELL STRUCTURES AND METHOD FOR FABRICATING SAME
Document Type and Number:
WIPO Patent Application WO2004095522
Kind Code:
A3
Abstract:
A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well (240) in a substrate, depositing an epitaxial layer over the substrate, and forming a P well (242) and a lateral isolation N well (246) over the deep N well, wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.

Inventors:
KAR-ROY ARJUN (US)
RACANELLI MARCO (US)
ZHANG JINSHU (US)
Application Number:
PCT/US2004/001877
Publication Date:
September 14, 2006
Filing Date:
January 24, 2004
Export Citation:
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Assignee:
NEWPORT FAB DBA JAZZ SEMICOND (US)
International Classes:
H01L21/74; H01L21/761; H01L21/8238; H01L27/092; (IPC1-7): H01L29/76
Foreign References:
US5899714A1999-05-04
US6617647B22003-09-09
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