This invention pertains to the field of complementary metal oxide semiconductor (CMOS) devices and, in particular, to electrically isolated medium voltage CMOS devices.

FIG. 1 shows a cross-sectional view of a semiconductor device 10 including two adjacent p-channel metal oxide semiconductor (PMOS) transistors 1 10 having channel regions 1 15 disposed in adjacent N-well regions 105 of a semiconductor substrate 100. Each of the transistors 1 10 comprises a source 112, a drain 114, and a gate electrode 116 extending between the source 1 12 and drain 1 14 and disposed on an oxide layer 1 18 on the semiconductor substrate 100. The transistors 1 10 are separated and isolated from each other by a field oxide region 120, typically formed by local oxidation of silicon (LOCOS) and therefore also sometimes referred to as a LOCOS oxide film 120.

When the semiconductor device 10 is a bulk silicon complementary MOS (CMOS) semiconductor device, each of these PMOS transistors 1 10 is associated with and connected to a corresponding n-channel MOS (NMOS) device (not shown).

The transistors 1 10 are "medium voltage transistors," which as used herein refers to transistors which are designed to operate at a maximum voltage of between ±3.5 V and ±20V for dual-supply operation, or at a maximum voltage of between +7 V to +40V for single-supply operation.

The field oxide region 120 separates and isolates the transistors 1 10 from each other. Therefore the field oxide region 120 must be designed such that when the transistors 1 10 are at their maximum operating voltages, the depletion regions of the transistors 1 10 do not "touch" each other. For a medium voltage CMOS transistor 110 with a maximum operating voltage range of 15 volts (and a breakdown voltage of 30 volts), the depletion region extends laterally and vertically into the semiconductor substrate 100 about 2.75 μm from the drain 1 14. Accordingly, in that case, the field oxide region 120 must have a width of at least 5.5 μm. So the distance between the drains 1 14 of the adjacent transistors 1 10 is necessarily greater than 5.5 μm.

Because of the requirement that the field oxide region 120 have a sufficient width to isolate the space charge regions of the adjacent transistors 1 10, transistor fabrication densities within the semiconductor device 10 are limited.

Accordingly, it would be desirable to provide a semiconductor device having a greater density of electrically isolated medium voltage transistors. It would also be desirable to provide an improved electrical isolation structure for devices in a semiconductor substrate. It would further be desirable to provide a method of fabricating electrically isolated medium voltage transistors with greater density.

In one aspect of the invention, a semiconductor device comprises a semiconductor substrate having a first impurity type; first and second well regions disposed adjacent each other within the semiconductor substrate and each having a second impurity type; a first source region and a first drain region in the first well region having a first channel region therebetween, each having the first impurity type; a second source region and a second drain region in the second well region having a second channel region therebetween, each having the first impurity type; a first gate disposed on the semiconductor substrate over the first channel region; a second gate disposed on the semiconductor substrate over the second channel region; a field oxide region on the semiconductor substrate extending between and separating the first and second drain regions; a trench extending from the field oxide region down to a depth greater than a depth of space charge regions of the first and second channels; and a dielectric material disposed in the trench.

Beneficially, the dielectric material is a thermal oxide. Also beneficially, the width of the field oxide region is less than 2 μm.

In another aspect of the invention, a semiconductor device comprises: a semiconductor substrate; first and second medium voltage MOS transistors each having a channel region in the semiconductor substrate; a field oxide region on the semiconductor substrate extending between and separating the first and second medium voltage MOS transistors; a trench extending from the field oxide region down to a depth greater than a depth of space charge regions of the first and second medium voltage MOS transistors; and a dielectric material disposed in the trench. Beneficially, the trench surrounds and isolates each of the first and second medium voltage MOS devices. Also beneficially, the width of the field oxide region is less than 2 μm.

In yet another aspect of the invention, a method of manufacturing a CMOS semiconductor device comprises: forming a field oxide layer on a the semiconductor substrate; forming a trench in the field oxide layer, where a width of the trench is less than a width of the field oxide layer such that the field oxide layer surrounds an upper periphery of the trench; forming an oxide material within the trench; and forming first and second medium voltage MOS transistors each having a channel region in the semiconductor substrate, said first and second medium voltage MOS transistors being isolated and separated from each other by the trench, wherein the trench extends from the field oxide region down into the semiconductor substrate to a depth greater than a depth of space charge regions of the first and second medium voltage MOS transistors.

Beneficially, forming the first and second medium voltage MOS transistors comprises forming first and second well regions in the semiconductor substrate, wherein the semiconductor substrate has a first conductivity type, the first and second well regions have a second conductivity type, the first medium voltage MOS transistor is formed in the first well region, and the second medium voltage MOS transistor is formed in the second well region.. Also beneficially, the width of the field oxide region is less than 2 μm.

FIG. 1 shows a semiconductor device having two MOS transistors separated by a field oxide region; FIG. 2 shows a semiconductor device having two MOS transistors separated by a field oxide region with a trench formed beneath.

FIG. 2 shows a cross-sectional view of a semiconductor device 20 including two adjacent p-channel metal oxide semiconductor (PMOS) transistors 210 having channel regions 215 formed in adjacent N-well regions 205 of a p-type semiconductor substrate 200. Each of the transistors 210 comprises a source 212, a drain 214, and a gate electrode 216 extending between the source 212 and drain 214 and disposed on an oxide layer 218 on the semiconductor substrate 200. The transistors 210 are separated and isolated from each other by a deep trench 230 in the semiconductor substrate 200. A field oxide region 220, typically formed by local oxidation of silicon (LOCOS) and therefore also sometimes referred to as a LOCOS oxide film 220, is on the top portion of the trench 230.

When the semiconductor device 20 is a bulk silicon complementary MOS (CMOS) semiconductor device, each of these PMOS transistors 210 is associated with and connected to a corresponding n-channel MOS (NMOS) device (not shown).

The transistors 210 are "medium voltage .transistors," which as used herein refers to transistors which are designed to operate at a maximum voltage of between ±3.5 V and ±20V for dual-supply operation, or at a maximum voltage of between +7V to +40V for single-supply operation.

Beneficially, the trench 230 is filled with a dielectric material, such as a thermal oxide (e.g., Siθ ₂ ) for surface state control. Even more beneficially, the trench is filled with a thermal oxide, Tetraethoxysilane (TEOS) on the thermal oxide, and a lightly-doped polysilicon material in the central core of the trench.

The trench 230 separates and isolates the transistors 210 from each other. Namely, the trench 230 prevents the depletion regions of the transistors 210 from "touching" each other. Beneficially, the trench 230 surrounds and isolates each of the wells 205 and/or the transistors 210.

Beneficially, the trench 230 extends down from the field oxide region 220 into the semiconductor substrate 200 to a depth that is greater than a depth of both of the depletion regions of the transistors 210. For a medium voltage CMOS transistor 210 with a maximum operating voltage range of 15 volts (and a breakdown voltage of 30 volts), the depletion region extends vertically about 2.75 μm from the drain 214 into the semiconductor substrate 200. Accordingly, in that case, beneficially the trench 230 has a depth from the top of the semiconductor substrate 200 that is about 2.75 μm or greater. Even more beneficially, the bottom of the trench 230 extends down below the bottoms of the N-well regions 205 into the doped semiconductor substrate 200. On the other hand, by virtue of the trench 230, the width of the field oxide region

220 can be reduced compared to the field oxide region 120 of device 10 of FIG. 1 which does not have the trench 230. Therefore, the distance between the adjacent transistors 210 of FIG. 2 can also be reduced compared to the distance between the adjacent transistors 1 10 of FIG. 1. For example, in the case where the medium voltage transistors 1 10 and 210 arte 15 volt devices, whereas the minimum width of the field oxide layer 120 of FIG. 1 must be about 5.5 μm, the width of the field oxide layer 220 of FIG. 2 can be less than 2.0 μm, indeed in this case only about 1.4 μm.

Accordingly, all other things being equal, the semiconductor device 20 can have a much greater density of transistors than the semiconductor device 10.

The semiconductor device 20 can be manufactured as follows. The substrate 200 having the LOCOS field isolation regions 220 are first formed. Then, the trenches 230 are formed in the LOCOS field isolation regions 220 such that the LOCOS field isolation region 220 always overlaps the trench 230. After etch, beneficially an oxide is thermally grown in the trenches 230. Also beneficially, a TEOS layer is formed in the trench on the thermal oxide, and a lightly-doped polysilicon is formed in a central core of the trench. Next, beneficially a chemical mechanical polishing (CMP) process is performed on the substrate. Then, the CMOS devices are fabricated according to a conventional process, such that adjacent devices are separated by the trenches 230.

While embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention. For example, although the device shown in FIG. 2 includes two PMOS transistors formed in two N- Wells of a p-type semiconductor substrate, the conductivity types of the wells, substrate, etc. can be changed or reversed. For example, the device could include two NMOS transistors formed in two P-wells in an n-type semiconductor substrate. Such variations would become clear to one of ordinary skill in the art after inspection of the specification, drawings and claims herein. The invention therefore is not to be restricted except within the spirit and scope of the appended claims.