DEFECT INSPECTION METHOD AND DEFECT INSPECTION DEVICE

WIPO Patent Application WO/2014/156262

A1

In order to reduce the amount of time it takes to collect images of defects, this defect inspection device is provided with the following: a read-out unit that reads out positions of defects in a semiconductor wafer that have already been detected; a first imaging unit that takes, at a first magnification, a reference image of a chip other than the chip where one of the read-out defects is; a second imaging unit that takes, at the first magnification, a first defect image that contains the read-out defect; a defect-position identification unit that identifies the position of the defect in the first defect image taken by the second imaging unit by comparing said first defect image with the reference image taken by the first imaging unit; a third imaging unit that, on the basis of the identified defect position, takes a second defect image at a second magnification that is higher than the first magnification; a rearrangement unit that rearranges the read-out defects in an order corresponding to a path that goes through each of the read-out defects exactly once; and a stage-movement-path generation unit that selects the chip where the reference image corresponding to each defect is to be taken and generates a stage-movement path by determining stage-movement positions for the first and second imaging units.

TAKAGI YUJI (JP)
HARADA MINORU (JP)
SAKAMOTO MASASHI (JP)
HIRAI TAKEHIRO (JP)

PCT/JP2014/051606

October 02, 2014

January 27, 2014

Click for automatic bibliography generation  

HITACHI HIGH TECH CORP (JP)

G01B15/00; G01B11/00; G01N23/225; H01L21/66; H01J37/22

JP5018868B2	2012-09-05
JP2005285746A	2005-10-13
JP2005302906A	2005-10-27
JPH0868772A	1996-03-12
JP2009283917A	2009-12-03

INOUE, Manabu et al. (JP)
Manabu Inoue (JP)

View/Download PDF      PDF Help

Previous Patent: COMMUNICATION SYSTEM

Next Patent: BATTERY SYSTEM