Title:
DEFECT OBSERVATION METHOD AND DEFECT OBSERVATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2014/119124
Kind Code:
A1
Abstract:
The purpose of the present invention is to easily extract, from samples to be observed, defect candidates that can be labeled as a defect or "nuisance" (a part for which a manufacturing tolerance or the like is erroneously detected) and to allow parameters pertaining to observation processing to be easily adjusted.
This defect observation method comprises: an imaging step to image, on the basis of defect information from an inspection device, an object to be inspected and obtain a defect image and a reference image corresponding to the defect image; a parameter determining step to determine a first parameter to be used in the defect extraction by using a first feature set distribution acquired from the reference image and the defect image captured in the imaging step and a second feature set distribution acquired from the reference image; and an observing step to observe using the first parameter determined in the parameter determining step.
The present invention can be applied to a method of observing defects generated during the manufacturing of semiconductor wafers.
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Inventors:
HARADA MINORU (JP)
TAKAGI YUJI (JP)
NAKAGAKI RYO (JP)
HIRAI TAKEHIRO (JP)
KITSUKI HIROHIKO (JP)
TAKAGI YUJI (JP)
NAKAGAKI RYO (JP)
HIRAI TAKEHIRO (JP)
KITSUKI HIROHIKO (JP)
Application Number:
PCT/JP2013/082753
Publication Date:
August 07, 2014
Filing Date:
December 06, 2013
Export Citation:
Assignee:
HITACHI HIGH TECH CORP (JP)
International Classes:
G01N23/225; G01N21/956
Foreign References:
| JP2007134498A | 2007-05-31 |
Other References:
MINORI NOGUCHI: "Current and Future View of Inspection and Metrology on Image Processing for Semiconductor", JOHO SHORI, vol. 51, no. 12, 15 December 2010 (2010-12-15), pages 1538 - 1546
YUICHIRO YAMAZAKI: "Metrology and inspection technologies for 32nm-generation semiconductor wafers", TOSHIBA REVIEW, vol. 64, no. 6, 1 June 2009 (2009-06-01), pages 39 - 43
YUICHIRO YAMAZAKI: "Metrology and inspection technologies for 32nm-generation semiconductor wafers", TOSHIBA REVIEW, vol. 64, no. 6, 1 June 2009 (2009-06-01), pages 39 - 43
Attorney, Agent or Firm:
INOUE, Manabu et al. (JP)
Manabu Inoue (JP)
Manabu Inoue (JP)
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