DEFECT OCCURRENCE PROCESS ANALYSIS DEVICE AND DEFECT OCCURRENCE PROCESS ANALYSIS METHOD

WIPO Patent Application WO/2014/097827

A1

This defect occurrence process analysis device is provided with: a mapping unit (521) which maps final defect information obtained in a final inspection process to coordinates set on a member according to defect type; an association unit (522) which associates intermediate defect information obtained in an intermediate inspection process and corrected result information obtained after a correction process for a defect detected in the intermediate inspection process has been performed with each other; a classification mapping unit (524) which, on the basis of the result of the classification of the intermediate defect information by a classification unit (523), maps the intermediate defect information to the coordinates set on the member according to the corrected result information; and a map display unit (525) which displays respective maps generated by the mapping unit (521) and the classification mapping unit (524) on the process-by-process basis. The present invention is applicable to manufacturing processes for an organic EL display panel and a liquid crystal display panel.

KYOHO MASANORI

PCT/JP2013/081641

June 26, 2014

November 25, 2013

Click for automatic bibliography generation  

SHARP KK (JP)

G01M11/00; G01N21/956; G02F1/13

JP2009264865A	2009-11-12
JP2008096302A	2008-04-24

YUJI TANAKA: "LCD Seizo Kotei ni Okeru Saishin Kensa Gijutsu", GEKKAN DISPLAY, vol. 12, no. 12, 1 December 2006 (2006-12-01), pages 30 - 34

SAMEJIMA, Mutsumi et al. (JP)
Mutsumi Sameshima (JP)

View/Download PDF      PDF Help

Previous Patent: VEHICULAR SHIFT OPERATION DEVICE

Next Patent: CONTROL DEVICE AND CONTROL METHOD FOR RANGE-TYPE TRANSMISSION