Title:
DELAY CIRCUIT, OSCILLATION CIRCUIT, AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2014/208470
Kind Code:
A1
Abstract:
Provided is a voltage regulator, wherein power consumption is small, and an NMOS transistor is used as an output transistor.
This delay circuit is configured by providing, between a constant current circuit and a capacitor, a depression NMOS transistor having the gate and the back gate thereof connected to a ground terminal, said constant current circuit being configured from a depression NMOS transistor and a resistor that is provided between the gate and the back gate, and the source of the depression NMOS transistor.
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| JP3027402 | [Name of invention] Signal delay circuit |
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Inventors:
NIHEI YOTARO (JP)
YOKOYAMA TOMOYUKI (JP)
YOKOYAMA TOMOYUKI (JP)
Application Number:
PCT/JP2014/066453
Publication Date:
December 31, 2014
Filing Date:
June 20, 2014
Export Citation:
Assignee:
SEIKO INSTR INC (JP)
International Classes:
H03K5/04; H03K3/03
Foreign References:
| JP2008271526A | 2008-11-06 | |||
| JP2003008410A | 2003-01-10 | |||
| JPH06224705A | 1994-08-12 | |||
| JPS54142962A | 1979-11-07 | |||
| JP2004260730A | 2004-09-16 |
Other References:
See also references of EP 3048727A4
Attorney, Agent or Firm:
UCHINO, Noriaki et al. (JP)
Noriaki Uchino (JP)
Noriaki Uchino (JP)
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