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Patent Searching and Data


Title:
DELAY CIRCUIT, OSCILLATION CIRCUIT, AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2014/208470
Kind Code:
A1
Abstract:
Provided is a voltage regulator, wherein power consumption is small, and an NMOS transistor is used as an output transistor. This delay circuit is configured by providing, between a constant current circuit and a capacitor, a depression NMOS transistor having the gate and the back gate thereof connected to a ground terminal, said constant current circuit being configured from a depression NMOS transistor and a resistor that is provided between the gate and the back gate, and the source of the depression NMOS transistor.

Inventors:
NIHEI, Yotaro (8 Nakase 1-chome, Mihama-ku, Chiba-sh, Chiba 07, 〒2618507, JP)
YOKOYAMA, Tomoyuki (829, Kichijima, Uozu-sh, Toyama 41, 〒9370041, JP)
Application Number:
JP2014/066453
Publication Date:
December 31, 2014
Filing Date:
June 20, 2014
Export Citation:
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Assignee:
SEIKO INSTRUMENTS INC. (8 Nakase 1-chome, Mihama-ku Chiba-sh, Chiba 07, 〒2618507, JP)
International Classes:
H03K5/04; H03K3/03
Foreign References:
JP2008271526A2008-11-06
JP2003008410A2003-01-10
JPH06224705A1994-08-12
JPS54142962A1979-11-07
JP2004260730A2004-09-16
Other References:
See also references of EP 3048727A4
Attorney, Agent or Firm:
UCHINO, Noriaki et al. (8 Nakase 1-chome, Mihama-ku, Chiba-sh, Chiba 07, 〒2618507, JP)
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