DELAY CIRCUIT - FUJITSU TEN LTD

Title:

DELAY CIRCUIT

Document Type and Number:

WIPO Patent Application WO/1979/000564

Kind Code:

A1

Abstract:

A delay circuit comprising counter circuits (32, 34), a flip-flop circuit (36), circuits (30, 40) for holding the flip-flop circuit in its reset situation for the duration of first signals (Xo, Yo) and a gate circuit (38) receiving a second signal (Sd) and operated by the output of the flip-flop circuit (36). According to this delay circuit, a relatively large delay may be easily accomplished in a digital Manner during the period up to the stoppage of output of a second signal after the termination of the first signal, even by the use of integrated circuits. This is adapted to be used for the tuning circuit for electronic-tuning type radio receivers.

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JPS5953725	[Title of the Invention] Receiving set
JPS62166678	CATV CONVERTER WITH TELEPHONE

Inventors:

ITO T (JP)

Application Number:

PCT/JP1979/000023

Publication Date:

August 23, 1979

Filing Date:

January 30, 1979

Export Citation:

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Assignee:

FUJITSU TEN LTD (JP)
ITO T (JP)

International Classes:

H03J5/00; H03J7/26; H03J7/28; H03K5/01; H03K5/13; H03K5/135; H03K17/28; H04B1/16; H04B1/26; (IPC1-7): H03K5/13; H03K5/01; H03K17/28; H03J5/00; H03B3/04

Foreign References:

JPS53163053U	1978-12-20
JPS4849919U	1973-06-30
JPS522349Y1	1977-01-19
JPS5133392A	1976-03-22
JPS445461B1
JPS5116082A	1976-02-09
JPS5081412A	1975-07-02
JPS4860511A	1973-08-24
JPS4613764B1

Other References: