Title:
DELAYED LOCKED LOOP CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/179920
Kind Code:
A1
Abstract:
[Problem] To control delay time with high accuracy. [Solution] A delayed locked loop circuit provided with: a first delay circuit that comprises at least one first delay device and at least one second delay device, the first delay devices and the second delay devices being connected in series; a second delay circuit that comprises third delay devices of the same number and the same configuration as the second delay devices, the third delay devices being connected to each other in series; a phase comparator that outputs a phase difference between a first delay clock obtained by a clock passing through the first delay circuit and being outputted from the first delay circuit, and a second delay clock obtained by the clock passing through the second delay circuit and being outputted from the second delay circuit; a first control circuit that in accordance with the phase difference, outputs a first control signal for controlling the time by which the clock is delayed in each of the first delay devices; and a second control circuit that outputs a second control signal for controlling the time by which the clock is delayed in each of the second delay devices and third delay devices.
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Inventors:
SOGA IKUO (JP)
OISHI KAZUAKI (JP)
MATSUMURA HIROSHI (JP)
KAWANO YOICHI (JP)
NAKASHA YASUHIRO (JP)
OISHI KAZUAKI (JP)
MATSUMURA HIROSHI (JP)
KAWANO YOICHI (JP)
NAKASHA YASUHIRO (JP)
Application Number:
PCT/JP2018/004823
Publication Date:
October 04, 2018
Filing Date:
February 13, 2018
Export Citation:
Assignee:
FUJITSU LTD (JP)
International Classes:
H03L7/081; H03K5/134; H04B1/04; H04L7/033
Foreign References:
| JP2006186547A | 2006-07-13 | |||
| JP2016082278A | 2016-05-16 | |||
| JP2000101425A | 2000-04-07 |
Attorney, Agent or Firm:
MUKOUYAMA, Naoki (JP)
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