Title:
DELTA SIGMA MODULATOR AND WIRELESS COMMUNICATION APPARATUS
Document Type and Number:
WIPO Patent Application WO/2010/058492
Kind Code:
A1
Abstract:
A delta sigma modulator has a loop along which an output signal from a quantizer is digital processed and then fed back to an analog filter via a DAC. In the delta sigma modulator, the quantizer (110) quantizes an analog signal from the analog filter part (100) to a digital signal. The digital signal from the quantizer (110) is digital processed by a first-order recursive filter circuit (125) comprising a variable gain (123) and a delay element (124). An LUT (121) receives as inputs the digital signal from the quantizer (110) and a table control signal (S1200), which is an output signal from the recursive filter circuit (125), to store a compensation value in accordance with these two signals in advance. The compensation value from the LUT (121) is a digital output signal in which the delay has been corrected, while this digital output signal is converted by the DAC (130) to an analog signal, which is then used to perform a subtraction from an analog input signal in the analog filter part (100). Thus, the influence of delay is reduced for high-speed wideband signals, whereby the precision of output signals can be improved.
Inventors:
MITANI YOSUKE
MATSUKAWA KAZUO
TAKAYAMA MASAO
DOSHO SHIRO
MATSUKAWA KAZUO
TAKAYAMA MASAO
DOSHO SHIRO
Application Number:
PCT/JP2009/001714
Publication Date:
May 27, 2010
Filing Date:
April 14, 2009
Export Citation:
Assignee:
PANASONIC CORP (JP)
MITANI YOSUKE
MATSUKAWA KAZUO
TAKAYAMA MASAO
DOSHO SHIRO
MITANI YOSUKE
MATSUKAWA KAZUO
TAKAYAMA MASAO
DOSHO SHIRO
International Classes:
H03M3/02
Foreign References:
| US20050068213A1 | 2005-03-31 | |||
| JP2005026998A | 2005-01-27 |
Other References:
PAUL FONTAINE ET AL.: "A Low-Noise Low-Voltage CT delta sigma Modulator with Digital Compensation of Excess Loop Delay", SOLID-STATE CIRCUITS CONFERENCE, 2005.DIGEST OF TECHNICALPAPERS.ISSCC.2005 IEEE INTERNATIONAL, vol. 1, - 10 February 2005 (2005-02-10), pages 498 - 499,613
JAMES A.CHERRY ET AL.: "Excess Loop Delay in Continuous-Time Delta-Sigma Modulators", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, vol. 46, no. 4, April 1999 (1999-04-01), pages 376 - 389
JAMES A.CHERRY ET AL.: "Excess Loop Delay in Continuous-Time Delta-Sigma Modulators", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, vol. 46, no. 4, April 1999 (1999-04-01), pages 376 - 389
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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