CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 13/919,747 filed June 17, 2013, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field:

[0002] The present disclosure relates generally to analog-to-digital converters and, more specifically, to analog-to-digital converters that receive low currents from voltage signals at their inputs.

2. Discussion of the Related Art:

[0003] Many electronic devices process information in the form of binary digits. The devices may be as complex as a smart mobile telephone or as simple as a controller for a household appliance. The binary digits often represent the value of an analog signal that the device receives as an input. In those devices that represent an analog input signal in digital form, an analog-to-digital converter may be used to translate the analog signal into a sequence of binary digits that may be processed by digital circuits. A common type of analog-to-digital converter uses a delta-sigma modulator to receive the analog signal.

[0004] A controller for an off-line power converter is one example of an electronic device that may use a delta-sigma modulator to receive an analog signal. In a controller for a power converter, the analog signal may represent the measurement of an input voltage that an analog- to-digital converter translates to a sequence of binary digits. The input voltage of an off-line power converter is typically a sinusoidal waveform with amplitude greater than 150 volts. In many parts of the world, the common household voltage that would be the input to an off-line power converter has a peak value greater than 300 volts, and may reach nearly 375 volts under transient conditions. Controllers often measure the input voltage for several purposes, such as, regulating an output voltage or shaping the waveform of an input current to follow the waveform of the input voltage.

l [0005] Circuits that measure a high input voltage typically do so by using a potential divider, such as a resistive divider, across the input to provide a known fraction of the input voltage as a signal voltage that is low enough for the measurement circuit to handle. In order to reduce power consumption, the components of the divider are selected to minimize the amount of current the circuit draws from the input voltage. However, the current needs to be large enough to guarantee a reliable measurement in the presence of noise.

[0006] A circuit, such as a common delta-sigma modulator, that measures the reduced-signal voltage provided by the potential divider, typically takes current from the voltage that it measures. Although the delta-sigma modulator takes current from the reduced- signal voltage provided by the potential divider, that current is obtained from the high voltage source of the input voltage and is passed through the potential divider. Since the power taken from the source of the input voltage is proportional to the product of the voltage and the current, and because the peak value of the input may be hundreds of volts, even the smallest current sufficient for reliable measurement can still result in a significant loss of power, especially when the power converter has a light load or no load.

[0007] Thus, since circuits with high input impedances take less current from a given voltage than a circuit with low input impedance, a delta-sigma modulator with high input impedance is desired to reduce the power consumption of circuits that measure relatively high voltages.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0009] FIG. 1 is a schematic diagram that shows the salient features of an example delta- sigma modulator with high input impedance according to various examples.

[0010] FIG. 2A and FIG. 2B are timing diagrams showing example waveforms that illustrate the operation of the example delta-sigma modulator shown in FIG. 1 for two different values of input voltage according to various examples. [0011] FIG. 3 A and FIG. 3B are equivalent circuits of a portion of the delta-sigma modulator of FIG. 1 illustrating the transfer of electric charge to and from the voltage of the input signal according to various examples.

[0012] FIG. 4 is a schematic diagram of an example delta-sigma modulator that uses MOS transistors as switches and capacitors according to various examples.

[0013] FIG. 5 is a timing diagram showing example waveforms that illustrate the relationships between clock signals in the example delta-sigma modulator of FIG. 4 according to various examples.

DETAILED DESCRIPTION

[0014] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.

[0015] Reference throughout this specification to "one embodiment," "an embodiment," "one example," or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment," "in an embodiment," "one example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

[0016] The schematic diagram of FIG. 1 illustrates an example measurement circuit 100 having a delta-sigma modulator that measures an analog input voltage V _I N 102 with respect to an input return 110. In some examples, measurement circuit 100 may be included within a controller for a power converter, and analog input voltage V _I N 102 may be the rectified input voltage to the power converter. The rectified input voltage may not go negative with respect to the input return 110, but may preserve the peak values of the sinusoidal input voltage. The example delta-sigma modulator in the measurement circuit of FIG. 1 includes a switched difference amplifier circuit 126, a switched-capacitor integrator circuit 128, and a switched comparator circuit 136. The "delta" in the name of the modulator is a reference to the difference amplifier, and the "sigma" in the name of the modulator is a reference to the integrator. The example measurement circuit 100 in the example of FIG. 1 may produce a digital output b ₀ 148 that is a sequence of logic high and logic low levels (binary digits) responsive to an analog signal voltage V _SI G at a node 106 that is representative of analog input voltage V _I N 102.

[0017] Also, by virtue of its switched-capacitor configuration, the electric charge received by the switched difference amplifier circuit 126 from node 106 at its input may be returned to node 106 such that the input to the delta-sigma modulator takes little to no average current from the voltage it measures. In other words, the delta-sigma modulator in the example measurement circuit of FIG. 1 may have a high input impedance by virtue of its switched-capacitor circuit configuration. Conventional delta-sigma modulators typically use a separate analog buffer amplifier to achieve high input impedance. Thus, the delta-sigma modulator of the present disclosure may achieve high impedance without the added cost of an analog buffer amplifier.

[0018] Although the analog input voltage V _I N 102 generally changes with time, its maximum rate of change is typically low enough to allow the output of the delta-sigma modulator to represent the input with negligible error. For example, in a typical power supply controller, the analog signal voltage V _SI G may have a maximum value of 4 volts, a minimum value of zero volts, and may change at the maximum rate of 1.5 volts per millisecond, whereas the output may produce about 1000 binary digits (bits) per millisecond. A sequence of less than 20 bits (corresponding to 30 millivolts in a range of 4 volts) is typically sufficient to represent the value of the analog signal voltage to control the power supply. Therefore, the analog input voltage may be assumed constant for the purposes of this explanation.

[0019] Measurement circuit 100 may include a potential divider and low pass filter formed by resistor Rl 104, resistor R2 108, and capacitor CF 112 to scale and filter the analog input voltage V _I N 102 to produce an analog signal voltage V _SI G at node 106 with respect to input return 110. The potential divider formed by resistor Rl 104 and resistor R2 108 reduces the magnitude of analog input voltage V _I N 102 to a lower value that the switched difference amplifier circuit 126 can safely accept.

[0020] The low-pass filter formed by capacitor CF 112 with resistor Rl 104 and resistor R2 108 further reduces the high frequencies in analog input voltage V _I N 102 that appear in analog signal voltage V _SI G at node 106. Reduction of high frequencies in the analog signal voltage V _SI G may be advantageous to the further processing of the digital output b ₀ 148 by other circuits. The low-pass filter is often referred to as an anti-aliasing filter and is generally used in analog-to- digital converters that use delta-sigma modulators. In other words, the presence of filter capacitor CF 112 is beneficial to the desired operation of the delta-sigma modulator, and analog signal voltage V _SI G at node 106 is a filtered input voltage. As will be explained later, filter capacitor CF 112 serves as a reservoir for electric charge that is received and delivered by the switched difference amplifier circuit 126.

[0021] For a given value of signal voltage V _SI G that is limited to be between a minimum boundary value VM _I N 8 and a maximum boundary value VMAX 114, the delta-sigma modulator in the example of FIG. 1 may produce an output b ₀ 148 that includes a repeating sequence of high and low logic levels, with the level being either high or low for the duration of each period of a clock signal Sc 150. Within the repeating sequence of high and low logic levels, the relative number of clock periods having a high logic level may correspond to the relative position of VSIG within the range of VMIN 118 to VMAX 114. For example, if VSIG is halfway between VMIN 118 and VMAX 114, the output b ₀ 148 may be a high logic level during half the clock periods. Similarly, if V _SI G is equal to VMAX 114, the output may be a high logic value during all the clock periods, and if V _SI G is equal to VM _I N 118, the output may be a low logic value during all the clock periods. In other words, the delta-sigma modulator modulates the density of high logic levels at its output in response to the relative position of a signal voltage between two boundary values.

[0022] In one example, the minimum boundary value VM _I N 118 may be zero. In examples where the minimum boundary value VM _I N 118 is zero, the density of high logic levels at the output b ₀ 148 is the ratio of the analog signal voltage V _SI G to the maximum boundary value VMAX 114.

[0023] The switched difference amplifier circuit 126 in the example of FIG. 1 includes a switched capacitor Csw 122 to transfer an amount of electric charge that corresponds to the difference between the analog signal voltage V _SI G at node 106 and one of the two boundary voltages VM _I N 118 and VMAX 114 during every period of the clock signal Sc 150. In a first portion of a clock period (e.g., first half cycle), the charge on capacitor Csw 122 is a first value that corresponds to the difference between a supply voltage VDD 132 and analog signal voltage V _SI G at node 106. In a practical application, the supply voltage VDD 132 may be greater than or equal to the maximum boundary value VMAX 114, although, in other examples, the supply voltage VDD 132 may be any voltage that is within the limitations of the components, including zero.

[0024] The switched-capacitor integrator circuit 128 may include an operational amplifier 133 that is configured to keep the voltages at its inputs substantially equal. The non- inverting input of operational amplifier 133 may be coupled to the supply voltage VDD 132. The voltage on the inverting input of operational amplifier 133 coupled to terminal 1 of single-pole double- throw (SPDT) switch S3 124 will also be at or near the voltage of the supply voltage VDD 132. Operational amplifier 133 may be a transconductance operational amplifier that produces an output current instead of an output voltage in response to a difference in voltage at its inputs. Thus, the voltage at the output of a transconductance operational amplifier is the result of the output current in the components coupled to the output.

[0025] In a second portion of the clock period (e.g., second half cycle), the charge on capacitor Csw 122 is a second value that corresponds to the difference between the supply voltage VDD 132 and either a lower boundary voltage VM _I N 118 or an upper boundary voltage VMAX 114. The change in electric charge on capacitor Csw 122 resulting from the change in voltage on capacitor Csw 122 within each clock period may accumulate on an integrating capacitor C _I N _T 130. The accumulated charge on integrating capacitor C _I N _T 130 is represented as an integral voltage V _I N _T 134 at the output of the switched-capacitor integrator 128.

[0026] Associating the accumulation of charge on integrating capacitor C _I N _T 130 with the state of the output b ₀ 148 allows the sequence of high and low logic levels of the output b ₀ 148 to represent the relationship of the analog signal voltage V _SI G to the boundary voltages VM _I N 118 and VMAX 144. In the example of FIG. 1, integrating capacitor C _I N _T 130 may either increase or decrease its charge in each period of clock signal Sc 150 by the amount required to change the voltage on switched capacitor Csw 122. The voltage on switched capacitor Csw 122 may change in each period of clock signal Sc 150 by an amount that depends on the logic level of output b ₀ 148. When clock signal Sc 150 is high, the voltage on switched capacitor Csw 122 may be equal (or at least substantially equal) to V _DD 132 minus V _S I _G - When clock signal Sc 150 is low, the integrator may force one terminal of switched capacitor Csw 122 to be at the voltage V _DD 132, and the other terminal of switched capacitor Csw 122 may be switched to either V _MIN 118 or V _MAX 114, depending on the logic level of output b ₀ 148. In other words, when clock signal Sc 150 goes low, the voltage on switched capacitor Csw 122 either increases by (VSI _G ^~ VMI _N ) if the output b ₀ 148 is a logic low level or decreases by (V _MAX - V _SIG ) if the output b ₀ 148 is a logic high level.

[0027] For the voltages (and the charges) on switched capacitor Csw 122 and integrating capacitor C _INT 130 to remain finite, the average change in voltage on each capacitor must be zero. A finite voltage (and charge) is maintained by comparing the integral voltage V _INT 134 to a reference voltage V _REF 138, with the result of the comparison causing the charge on switched capacitor Csw 122 to decrease or increase so that the integral voltage V _INT 134 changes in a direction toward the value of the reference voltage V _REF 138 in every period of clock signal Sc 150. In some periods of clock signal Sc 150, the integral voltage V _INT 138 may cross the value of the reference voltage V _REF 138, moving away from the reference voltage V _REF 138 in the opposite direction, only to change direction toward the reference voltage V _REF 138 again in the next clock period. In practical applications, the reference voltage V _REF 138 may be a value midway between the minimum boundary voltage V _MIN 118 and the supply voltage V _DD 132.

[0028] The comparator 140 of switched comparator circuit 136 may be used to compare the integral voltage V _INT 134 to a reference voltage V _REF 138. Switched comparator circuit 136 further includes a D flip-flop 144 coupled to receive output signal 142 from comparator 140 and a clock input 146, which may be an inverted clock signal Sc 150 from inverter 152. In the example of FIG. 1, D flip-flop 144 outputs the digital output b ₀ 148 at a high logic level if the integral voltage V _INT 134 is greater than the reference voltage V _REF 138 and at a low logic level if the integral voltage V _INT 134 is not greater than the reference voltage V _REF 138. The result is that the average voltage applied to one terminal of switched capacitor Csw 122 is V _DD 132, and the average voltage applied to the other terminal of switched capacitor Csw 122 is V _SIG - In other words, in a repeating sequence of high and low logic levels on the output b ₀ 148, V _MAX 144 is applied during each output high level and V _MIN 118 is applied during each output low level when clock signal Sc 150 is low so that the average voltage applied to one side of the capacitor is V _SIG - [0029] It will now be explained in further detail how the circuit in the example of FIG. 1 produces a sequence of high and low logic levels such that the density of high logic levels is substantially equal to the relative proximity of analog voltage V _SI G to the upper boundary voltage VMAX 114 within the range between the lower boundary voltage VM _I N 8 and the upper boundary voltage VMAX 114.

[0030] The example of FIG. 1 shows a switched capacitor Csw 122 and SPDT switches SI 116, S2 120, and S3 124. A single-pole double-throw switch has one pole terminal that may be coupled to either of two switched terminals. One terminal of switched capacitor Csw 122 in the example of FIG. 1 is coupled to the pole terminal of SPDT switch S2 120. The other terminal of switched capacitor Csw 122 is coupled to the pole terminal of another SPDT switch S3 124.

[0031] The system clock signal Sc 150 alternates between a high logic level and a low logic level within regular consecutive clock periods. In the example of FIG. 1, clock signal Sc 150 is low during the first half of a clock period and is high during the second half of the clock period. In the example of FIG. 1, switch S2 120 and switch S3 124 are in a first position (pole terminal coupled to switched terminal 1) when clock signal Sc 150 is low; switch S2 120 and switch S3 124 are in a second position (pole terminal coupled to switched terminal 2) when clock signal Sc 150 is high.

[0032] In the example of FIG. 1, switched terminal 1 of SPDT switch S2 120 is coupled to the pole terminal of SPDT switch SI 116. Boundary voltages VMAX 114 and VM _I N 118 are coupled respectively to switched terminal 1 and switched terminal 2 of SPDT switch SI 116. Switch SI 116 is in a first position (pole terminal coupled to switched terminal 1) when the output b ₀ 148 is at a high logic level, and switch SI 116 is in a second position (pole terminal coupled to switched terminal 2) when output b ₀ 148 is at a low logic level.

[0033] In other words, during a portion of the clock period when clock signal Sc 150 is high, switched capacitor Csw 122 is coupled between the signal voltage V _SI G at node 106 and a supply voltage VDD 132. During a portion of the clock period when clock signal Sc 150 is low, switched capacitor Csw 122 is coupled between a terminal of an integrating capacitor C _I N _T 130 and a boundary voltage that is either a maximum voltage VMAX 114 when the output b ₀ 148 is a high logic level or is a minimum voltage VM _I N 118 when the output b ₀ 148 is a low logic level. The boundary voltage may be considered an offset voltage, and the switched difference amplifier circuit 126 may be considered to output a switched difference voltage that is representative of the variable offset voltage plus a difference between the filtered input voltage V _SI G and supply voltage VDD 132.

[0034] Example waveforms of selected signals from the example circuit of FIG. 1 are shown in FIG. 2A and FIG. 2B for two different values of analog signal voltage V _SI G within the range of values between the lower boundary VM _I N 1 18 and the upper boundary VMAX 1 14. FIG. 2A is a timing diagram 200 that illustrates the output b ₀ 148 when the difference between V _SI G and VM _I N 1 18 is seven sixteenths the difference between VMAX 1 14 and VM _I N 1 18. FIG. 2B is a timing diagram 250 that illustrates the output b ₀ 148 when the difference between V _SI G and VM _I N is seventeen twentieths the difference between VMAX and VM _I N-

[0035] In the example of FIG. 2A, integral voltage V _I N _T 134 and output b ₀ 148 are shown with clock signal Sc 150 that has a period Tc 205. Output b ₀ 148 is a repeating sequence of high and low logic levels having a period T _b 210 that includes 16 clock periods T _c 205. Within every period T _b 210, the output b ₀ 148 is a high logic level in seven of the sixteen clock periods, and the output b ₀ 148 is a low logic level in nine of the sixteen clock periods. In other words, the density of high logic levels D _H is 7/16, and the density of low logic levels D _L is 9/16. The sum of D _H and D _L is unity (D _H + D _L = 1).

[0036] FIG. 2A shows that the integral voltage V _I N _T 134 changes in a direction toward the value of the reference voltage V _RE F 138 in every period of clock signal Sc 150. In most periods of clock signal Sc 150 in the example of FIG. 2A, the integral voltage V _I N _T 134 crosses the value of the reference voltage V _RE F 138, moving away from it in the opposite direction, only to change direction toward the reference again in the next clock period.

[0037] The example of FIG. 2B shows integral voltage V _I N _T 134 and output b ₀ 148 with clock signal Sc 150 that has a period T _c 205 for an analog signal voltage V _SI G that is larger than the value of analog signal voltage V _SI G in FIG. 2A. Output b ₀ 148 in the example of FIG. 2B is a repeating sequence of high and low logic levels having a period T _b 215 that now includes 20 clock periods T _c 205. Within every period T _b 215, the output is a high logic level in 17 of the 20 clock periods, and the output is a low logic level in three of the 20 clock periods. In other words, the density of high logic values D _H is 17/20, and the density of low logic values D _L is 3/20. The sum of D _H and D _L is unity (D _H + D _L = 1).

[0038] FIG. 2B, like FIG. 2A, shows that the integral voltage V _I N _T 134 changes in a direction toward the value of the reference voltage V _RE F 138 in every period of clock signal Sc 150. In the example of FIG. 2B the integral voltage V _I N _T 134 crosses the value of the reference voltage V _RE F 138, moving away from it in the opposite direction, in only three of the 20 clock periods of an output sequence T _b 215. In other words, the switched-capacitor integrator circuit 128 is coupled to receive the switched difference voltage and is configured to output an integral voltage V _I N _T 134 based on a difference between the switched difference voltage and the supply voltage VDD 132. Furthermore, the switched comparator circuit 136 is coupled to receive the integral voltage V _I N _T 134 and is configured to output an output signal b ₀ 148 based on a difference between the switched difference voltage and a reference voltage V _RE F 138.

[0039] The schematic diagrams of FIG. 3 A and FIG. 3B are equivalent circuits of a portion of the delta-sigma modulator in FIG. 1 that illustrate the feature of high input impedance. The equivalent circuit 300 in FIG. 3A shows the switched capacitor Csw 122 with one terminal coupled to a voltage source VDD 332 and the other terminal coupled to a voltage source VMAX 314 through switch S4 316 and switch S5 320. The equivalent circuit in FIG. 3A corresponds to the condition in FIG. 1 where the output b ₀ 148 is at a high logic level and the clock signal Sc 150 is at a low logic level. When clock signal Sc 150 changes to a high logic level, the pole terminal of switch S5 320 will switch from terminal 1 to terminal 2, and voltage source V _SI G 306 will receive an electric charge QH that is the product of Csw multiplied by the difference of VMAX minus V _S IG-

[0040] The equivalent circuit 350 in FIG. 3B shows the switched capacitor Csw 122 with one terminal coupled to a voltage source VDD 332 and the other terminal coupled to a voltage source VM _I N 318 through switch S4 316 and switch S5 320. The equivalent circuit in FIG. 3B corresponds to the condition in FIG. 1 where the output b ₀ 148 is at a low logic level and the clock signal Sc 150 is at a low logic level. When clock signal Sc 150 changes to a high logic level, the pole terminal of switch S5 320 will switch from terminal 1 to terminal 2, and voltage source V _SI G 306 will deliver an electric charge QL that is the product of Csw multiplied by the difference of VSIG minus VMIN-

[0041] For a repeating sequence of values of output b ₀ 148, the total charge received by voltage source V _SI G 306 is the density of high logic levels D _H multiplied by the charge QH, and the total charge taken from voltage source V _SI G 306 is the density of low logic levels D _L multiplied by the charge QL. Since the sum of D _H and D _L is unity, it is straightforward to show that voltage source V _SI G provides no net charge in a repeating sequence of the output b ₀ 148. If QAVE is the average charge taken from voltage source VSIG 306, we can write from FIG. 3A and FIG. 3B

Q _AVE = D _L Q _L - D _H Q _H (1) [0042] Substituting for the density of low logic levels D _L gives

Q _AVE = - D _H Q _L - D _H Q _H (2) [0043] which can be rearranged as

Q _AVE = Q _L - D _H (Q _L + Q _H ) (3) [0044] Substituting for Q _L , QH, and D _H gives

QAVE — CSW(VSIG CSW(VSIG VMIN + VMAX VSIG) (4)

[0045] that simplifies to

QAVE — CSW(VSIG ^MIN) CSW(VSIG ^MIN) (5)

[0046] and

[0047] to show that the average charge removed from voltage source VSIG 306 is zero. The current provided by a voltage source is the rate that charge is removed from the voltage source. In other words, the average current provided by voltage source VSIG 306 is zero. In the example of FIG. 1, filter capacitor CF 112 has the role of a voltage source that provides charge QL and accepts charge QH SO that node 106 remains substantially at the fraction of the input voltage VIN 102 as determined by Rl 104 and R2 108 while providing no average current to the input of delta- sigma modulator.

[0048] The example delta-sigma modulator of FIG. 1 may be realized in an integrated circuit that uses metal-oxide semiconductor field-effect transistors (MOSFETs) for the switches and also for the capacitors. A practical circuit that cannot charge capacitors instantaneously and that must allow finite time for circuits to respond may benefit from a multiphase clock that has built- in delays to allow for the response of non-ideal components. FIG. 4 is a schematic diagram 400 of an example implementation of the delta-sigma modulator of FIG. 1 using MOSFETs and a four-phase clock. FIG. 5 is a timing diagram 500 showing the phases of the four-phase clock with respect to the output in the example circuit of FIG. 4.

[0049] In the example of FIG. 4, p-channel metal-oxide semiconductor (PMOS) transistors 422 and 430 form, respectively, the switched capacitor Csw 122 and the integrating capacitor CiNT 130 of FIG. 1. Each of PMOS transistors 422 and 430 has a gate terminal G, a drain terminal D, a source terminal S, and a bulk terminal B. Drain, source, and bulk terminals are coupled together at a node that is one terminal of the capacitor, and the gate terminal of the PMOS transistor is the other terminal of the capacitor. The capacitance of the PMOS transistors is linear when the transistors operate in the enhancement mode with the gate voltage more than a threshold voltage below the source voltage. Therefore, the transistors are oriented so the terminal coupled to the drain, source, and bulk has the higher voltage, and the voltages are selected to keep the PMOS transistors in their linear region.

[0050] N-channel metal-oxide semiconductor (NMOS) transistors 472, 474, 476, 478, and 480 with their bulk terminals coupled to their source terminals form single-pole single-throw (SPST) switches that can conduct when the voltage on the gate terminal with respect to the source terminal is greater than a threshold voltage. Transistors 478 and 480 with appropriate signals at their respective gates 466 and 450 form SPDT switch S3 124 of FIG. 1. Similarly, transistors 472, 474, and 476 with appropriate signals at their respective gates form the SPDT switches SI 116 and S2 120 of FIG. 1.

[0051] A four-phase clock provides the appropriate signals to switch the transistors in the example of FIG. 4. The phases of the clock are designated as φΐ, φΐά, φ2, and φ2ά. The clock signals are illustrated in the timing diagram 500 of FIG. 5. Two complete clock periods of duration T _C LK are illustrated relative to the output b ₀ 448.

[0052] During each clock period T _C LK, each phase of the clock is at a high logic level for a duration TH followed by a low logic level for a duration TL. The high logic level TH of φ2 466 occurs during the low logic level T _L of φΐ 458. Clock signal φΐά 458 is clock signal φΐ 450 delayed by an interval Τ _< π. Clock signal φ2ά 470 is clock signal φ2 466 delayed by an interval Td2. The delays are chosen as appropriate to accommodate the response times of the elements in the circuit. [0053] The example circuit of FIG. 4 shows a first switch 472 controlled by the output b ₀ 448 and clock signal φ2ά 470 as inputs to an AND gate 460 that has its output coupled to the gate terminal of transistor 472. First switch 472 couples a first voltage that is the maximum boundary voltage VMAX 414 to a first terminal of switched capacitor Csw 422.

[0054] The example circuit of FIG. 4 shows a second switch 474 controlled by clock signal φΐά 468. Second switch 474 couples the filtered input voltage V _SI G 406 to the first terminal of switched capacitor Csw 422.

[0055] The example circuit of FIG. 4 shows a third switch 476 controlled by clock signal (|)2d 470 and inverted output 464 as inputs to an AND gate 462 that has its output coupled to the gate terminal of transistor 476. Third switch 476 couples a second voltage that is the minimum boundary voltage VM _I N 418 to the first terminal of switched capacitor Csw 422. The minimum boundary voltage VM _I N 418 in the example of FIG. 4 is zero, since it is common with the input return 410. In summary, the switched difference amplifier circuit is configured to output the switched difference voltage by selectively coupling a first terminal G of a switched capacitor Csw 422 to receive the filtered input voltage V _SI G 406, a first voltage VMAX 414, and a second voltage VM _I N 418. Furthermore, the switched difference voltage comprises a voltage at a second terminal B of the switched capacitor Csw 422.

[0056] Transconductance operational amplifier 433 in the example of FIG. 4 forms an integrator with integrating capacitor C _I N _T 430. The non-inverting input of transconductance operational amplifier 433 is coupled to a supply voltage VDD 432, and the inverting input of transconductance operational amplifier 433 is coupled to integrating capacitor C _I N _T 430.

Capacitors C _nl 482 and C^ 484 are relatively small NMOS capacitors that limit the amplitude of transient voltages during switching to less than a MOSFET threshold voltage above the supply voltage VDD, preventing loss of charge from the PMOS capacitors Csw 422 and C _I N _T 430.

[0057] In the example of FIG. 4, an integral output voltage V _I N _T 434 is received at the non- inverting input of a latching analog comparator 440 that compares the integral output voltage V _I N _T 434 to a reference voltage 438 at its inverting input. Latching analog comparator 440 latches the result of the comparison at its inputs when LATCH ENABLE signal 468 from the output of an inverter 454 goes to a high logic level, which is when the clock signal φ2 466 goes to a low logic level. [0058] The output of latching analog comparator 440 is received by a D flip-flop 444 that sets the state of its outputs 448 and 464 when its clock input 446 goes to a high logic level. An inverter 452 inverts clock signal φΐ 450 to become the clock input 446 to D flip-flop 444.

[0059] In one example, the supply VDD 432 is 5.3 volts, the maximum boundary voltage VMAX 414 is 4 volts, the minimum boundary voltage VM _I N 418 is zero volts, and the reference voltage V _RE F 438 is 2.6 volts. In the same example, switched capacitor Csw 422 is 0.25 picofarads, integration capacitor C _I N _T 430 is 0.75 picofarads, C _nl 482 and C^ 484 are 0.5 picofarads. However, it should be appreciated that other values may be used depending on the application.

[0060] The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention.

[0061] These modifications can be made to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.