Title:
DESIGN ASSISTANCE SYSTEM, DESIGN ASSISTANCE METHOD, AND PROGRAM RECORDING MEDIUM
Document Type and Number:
WIPO Patent Application WO/2019/107234
Kind Code:
A1
Abstract:
In order to enable designing of a highly reliable programmable logic integrated circuit, this design assistance system is provided with: a logic synthesis unit that receives input of an operation description file of the programmable logic integrated circuit, logically synthesizes the inputted operation description file, and generates a net list by using logic elements included in the programmable logic integrated circuit; an arrangement wiring unit that generates resource information of the programmable logic integrated circuit, arranges the logic elements included in the net list on the basis of the generated resource information, and virtually generates a signal path by laying wires among the arranged logic elements; and a reliability control unit that generates configuration information of the programmable logic integrated circuit on the basis of at least two reliability modes, and outputs the generated configuration information.
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Inventors:
NEBASHI RYUSUKE (JP)
SAKAMOTO TOSHITSUGU (JP)
MIYAMURA MAKOTO (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
BAI XU (JP)
SAKAMOTO TOSHITSUGU (JP)
MIYAMURA MAKOTO (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
BAI XU (JP)
Application Number:
PCT/JP2018/042926
Publication Date:
June 06, 2019
Filing Date:
November 21, 2018
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
G06F17/50; H01L21/82
Domestic Patent References:
| WO2016194332A1 | 2016-12-08 |
Foreign References:
| JP2012221077A | 2012-11-12 | |||
| JPH04345210A | 1992-12-01 |
Attorney, Agent or Firm:
SHIMOSAKA Naoki (JP)
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