Title:
DESIGN CONDITION COMPUTATION SYSTEM AND METHOD FOR MANUACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/100432
Kind Code:
A1
Abstract:
This design condition computation system comprises an optimized computation unit that, using models built by a model building unit, computes a first parameter and a second parameter so that a predetermined condition is satisfied. Of the models built by the model building unit: a first conversion model provided in a front stage converts at least one of the first and second parameters into a physical value that is input to a property regression model; the property regression model, which is provided in the middle, converts an unobservable physical value into an unobservable theoretical property value; and a second conversion model provided in a later stage converts the theoretical property value into an actual property value, and, using the built models and using a fixed value set in a part of the first and second parameters as a constraint condition, computes first and second parameters that are not constraint conditions so as to satisfy a condition due to one or a combination of the value and range of a third parameter.
Inventors:
SUEMATSU TOMOKA (JP)
SUTO TAKERU (JP)
KOBAYASHI KEISUKE (JP)
MORI YUKI (JP)
SHIMA AKIO (JP)
SUTO TAKERU (JP)
KOBAYASHI KEISUKE (JP)
MORI YUKI (JP)
SHIMA AKIO (JP)
Application Number:
PCT/JP2022/033324
Publication Date:
June 08, 2023
Filing Date:
September 05, 2022
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
H01L29/00; G06F30/3308; G06F30/367; H01L21/00; H01L21/336; H01L29/78
Foreign References:
JP2021100039A | 2021-07-01 | |||
JP2020184123A | 2020-11-12 | |||
JP2019003651A | 2019-01-10 | |||
JP2012064154A | 2012-03-29 |
Attorney, Agent or Firm:
TOU-OU PATENT FIRM (JP)
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