CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to US provisional application serial no.

62/081,724, filed November 19, 2014, by Andrew J. Gardner and Jeffrey L. Heath.

FIELD OF THE INVENTION

This invention relates to Power over Data Lines (PoDL) systems, where power from a Power Sourcing Equipment (PSE) is transmitted to a Powered Device (PD) over a single wire pair that is also used for conducting differential data signals, typically

Ethernet signals. The invention particularly relates to detecting ground isolation faults between the PSE and PD.

BACKGROUND

It is known to transmit Power over Data Lines to remote power equipment. Power over Ethernet (PoE) is an example of one such system. In PoE, limited power is transmitted to Ethernet-connected equipment (e.g., VoIP telephones, WLAN transmitters, security cameras, etc.) from an Ethernet switch. DC power from the switch is transmitted over two or more twisted wire pairs in the standard CAT-n cabling. One or more of the wire pairs also transmit differential data signals, since the DC common mode voltage does not affect the data. In this way, the need for providing any external power source for the Powered Devices (PDs) can be eliminated.

A newer technology is Power over Data Lines (PoDL) where power is transmitted over a single, twisted wire pair along with the differential data. As of the date of this disclosure, the IEEE is in the process of developing a standard for PoDL as IEEE

802.3bu. PoDL may be more flexible than PoE and, since it requires just one wire pair, is likely to become a popular technique, especially in automobiles.

It is envisioned that PoDL applications will require some manner of isolation between the PD ground and the PSE ground in order to prevent the formation of or minimize the effects of ground loops. The grounds are the respective reference nodes for the PSE and PD and are not necessarily absolute grounds or equal to each other. While failure of the PSE ground to PD ground isolation may not result in outright functional failure of the PoDL link, the resulting current flow (leakage current) may substantially degrade the integrity of the Ethernet data. Hence the ability to detect a failure in the isolation between the PD ground and PSE ground is important in order ensure data integrity in a PoDL Ethernet link.

SUMMARY

Circuits and techniques are described for detecting a ground fault leakage current between the PSE and the PD, both prior to the PoDL voltage being applied to the PD and after the PoDL voltage has been applied to the PD.

In one embodiment, prior to the PoDL voltage being applied to the PD, a fault test switch is temporarily closed to sense a voltage drop across a portion of the current loop between the positive terminal of the PSE voltage source and any ground leakage path between the PSE and the PD. If the resistance of the ground leakage path is below a certain threshold, a fault signal is generated.

In another embodiment, a similar test may be performed without a test switch by temporarily supplying a known test current through the current loop and sensing the voltage drop to determine if the resistance of the ground leakage path is below a certain threshold.

In another embodiment, the positive terminal of the PSE voltage source is temporarily connected to the current loop and the resulting current is sensed.

Other circuits are described.

To detect a ground isolation fault between the PSE and the PD after the full PoDL voltage is applied to the PD, the source and return PSE currents are sensed, differenced, and compared against a window in order to detect a ground isolation fault while the link is powered.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a PoDL system that includes circuitry for detecting a ground isolation fault between the PSE and PD, prior to the PoDL voltage being applied to the PD, in accordance with a first embodiment of the invention.

Fig. 2 illustrates a PoDL system that includes circuitry for detecting a ground isolation fault between the PSE and PD, prior to the PoDL voltage being applied to the PD, in accordance with a second embodiment of the invention.

Fig. 3 illustrates a PoDL system that includes circuitry for detecting a ground isolation fault between the PSE and PD, prior to the PoDL voltage being applied to the PD, in accordance with a third embodiment of the invention.

Fig. 4 illustrates a PoDL system that includes circuitry for detecting a ground isolation fault between the PSE and PD, prior to the PoDL voltage being applied to the PD, in accordance with a fourth embodiment of the invention.

Fig. 5 illustrates a PoDL system that includes circuitry for detecting a ground isolation fault between the PSE and PD, prior to the PoDL voltage being applied to the PD, in accordance with a fifth embodiment of the invention.

Fig. 6 illustrates a PoDL system that includes circuitry for detecting a ground isolation fault between the PSE and PD, after the PoDL voltage has been applied to the PD, in accordance with a sixth embodiment of the invention.

Elements that are the same or equivalent in the various figures are labeled with the same numeral.

DETAILED DESCRIPTION

Various PoDL systems are described that include circuitry for detecting a ground isolation fault between the PSE and PD. Generally, such a ground fault creates an unintended current path (a loop) between the PD's negative reference voltage terminal and the PSE's ground terminal. The amount of such leakage is detected by the disclosed circuits and, if the leakage is above a certain threshold, a ground fault is declared. This fault signal may then be used to disable the PoDL system since the Ethernet data may be compromised.

Conventional aspects of a PoDL will first be described with respect to Fig. 1. Fig. 1 illustrates the pertinent portion of a PSE 10 and a PD 12 connected via a first wire 14 and a second wire 16 in a twisted wire pair 18.

A coupling/decoupling network comprises capacitors C1-C4 and inductors L1-L4. The relatively high frequency Ethernet differential data is passed by the capacitors C1-C4 while the inductors L1-L4 block the data signals. The Ethernet transceivers are referred to as PHYs, which are the physical layers in the data path. The data is processed by conventional equipment not shown in the figures.

The PoDL DC voltage that powers the PD 12 is generated by a PSE voltage source 20 generating the voltage VPSE- Once the power switches 21 and 22 are closed, the DC voltage is coupled to the wire pair 18 by the inductors LI and L2, and the DC voltage is coupled to the PD load, represented by the resistor RPD, via the decoupling inductors L3 and L4. The capacitors C1-C4 block the DC voltage. A capacitor CPD smooths the DC voltage.

Typically, in a PoDL system, a low power detection and classification routine is performed that detects whether the PD is PoDL-compatible and conveys the power requirements of the PD. This low power routine will be referred to as handshaking and is described in the IEEE standards for PoDL. Such a routine may be carried out by a state machine, a processor, or other known circuits and is represented by the

Detection/Classification circuit 23. Prior to a successful handshaking, power switches 21 and 22 between the PSE voltage source 20 and the twisted wire pair 18 are open. After a successful handshaking, the power switches 21 and 22 are closed to supply the full PoDL voltage VPSE to the PD 12.

It is possible that the negative terminal of the PD 12 can be shorted to the ground of the PSE 10 or have some other level of leakage to the ground of the PSE 10. Such current leakage between the negative terminal of the PD 12 and the ground of the PSE 10 may substantially degrade the integrity of the Ethernet data. Therefore, it is important that a ground isolation fault is identified if the current leakage is near a level where the Ethernet data becomes unreliable. Three possible scenarios exist for detecting ground fault current leakage loops between the PSE and PD in Ethernet PoDL: 1) detection prior to the application of PoDL power to the PD; 2) detection in the presence of PoDL power being applied to the PD; or 3) both.

Figs. 1-5 illustrate alternative circuitry and schemes for detecting a ground isolation fault prior to the PoDL voltage being applied to the PD 12. In Fig. 1, after start-up but prior to the power switches 21 and 22 being closed, a fault test switch 24 is temporarily closed to couple a pull-up test resistor R _tes t between the positive terminal of the PSE voltage source 20 and the inductor L2. The voltage across the test resistor R _tes t is sensed by a differential amplifier 26, which outputs a voltage sense signal V _se nse- _se nse is then compared to a fixed voltage threshold Va, by a hysteresis comparator 28. If V _sen se is greater than Va,, taking into account the hysteresis, a ground isolation fault signal is generated. This fault signal may then be used to signal that the system needs servicing to fix the ground isolation fault. The fault signal may also disable the system to prevent the power switches 21 and 22 being closed.

The ground isolation leakage resistance is represented by the resistance Ri _ea k- The lower the Ri _ea k resistance, the more current leakage there is between the PD 12 ground and the PSE 10 ground. When the fault test switch 24 is closed, a current loop is created by the resistor R _test , inductor L2, wire 16, inductor L4, and Ri _ea k to the PSE 10 ground. Resistances R _tes t and Ri _ea k form a voltage divider in the leakage current loop.

The V _S ense is given by V _se nse = Vps _E xRtest/(Rtest+Rieak), assuming there is negligible resistance from inductors L2, L4, and wire 16. As the value of Ri _ea k decreases, the value of Vsense will increase to a maximum value of VPSE in the event of a full ground short. By comparing V _se nse against the threshold voltage Va,, set between VPSE and 0V, it is detected when the leakage resistance Ri _ea k between PSE ground and the negative voltage PD terminal has decreased below a critical value. The critical value may be determined by the leakage resistance needed to sufficiently degrade the Ethernet data. The fault signal is then asserted. The fault signal may disable the power switches 14 and 16 from being turned on.

If the resistance from inductors L2 and L4 and wire 16 is substantial, this needs to be taken into account when selecting the acceptable level of V _se nse- Additional embodiments for test and measurement of the leakage path resistance or current between the PD and PSE with open PSE source and return power switches 21 and 22 are illustrated in Figs. 2-5.

In Fig. 2, a fault test current source 32, connected between the positive terminal of the voltage source 20 and the inductor L2, is temporarily turned on to supply a fixed current through the current loop created by inductor L2, wire 16, inductor L4, and Ri _ea k to the PSE ground. The voltage drop across the series combination of the resistance Ri _ea k, inductors L2 and L4, and wire 16 is detected by a differential amplifier 34 to generate a voltage sense signal V _se nse having a known relationship to the value of Ri _ea k- _se nse is then applied to a hysteresis comparator for comparison to a threshold voltage, in the manner shown in Fig. 1 , to generate a fault signal if the value of Ri _ea k is below a threshold value.

Fig. 3 illustrates an embodiment that directly senses the leakage current between the positive terminal of the voltage source 20 and the PSE ground, via the inductors L2 and L4, wire 16, and resistance Ri _ea k, when a fault test switch 36 is temporarily closed prior to the power switches 21 and 22 being turned on. The current I _sen se may be sensed by a low value sense resistor in series with the current path, where the voltage drop across the sense resistor is related to the current. Such a conventional current sense circuit is represented by the current sense circuit 38 that outputs the value I _se nse- A voltage corresponding to I _sen se is then compared to a threshold voltage, in the same manner shown in Fig. 1, and a fault signal is asserted by the comparator if the leakage current is above a threshold that would sufficiently degrade the Ethernet data.

Fig. 4 illustrates an embodiment where the positive terminal of the PSE voltage source 20 is coupled to the inductor LI and wire 14, via a sense resistor R _se nse, when a fault test switch 40 is temporarily closed when the power switches 21 and 22 are open. The current loop between the positive terminal and the PSE ground is therefore through the sense resistor R _se nse, inductor LI, wire 14, inductor L3, the PD load RPD, and the ground fault resistance Ri _ea k- The voltage drop across the sense resistor R _se nse is detected by a differential amplifier 42 to generate V _se nse, and V _se nse is compared to a threshold voltage, in the manner shown in Fig. 1 , to determine whether a fault signal is to be asserted.

Fig. 5 illustrates an embodiment where a current source 46, coupled to the positive terminal of the voltage source 20, is temporarily turned on to supply a fixed current I _tes t through a first current loop, comprising inductor LI , wire 14, inductor L3, the PD load Rp _D , and the ground fault resistance Ri _eak> and simultaneously through a second current loop that includes inductor L4, wire 16, and inductor L2.

If the ground isolation leakage resistance_Ri _eak is high (e.g., an open circuit), all current will flow through the second loop that includes inductor L4, wire 16, and inductor L2. As a result, the voltage difference at the inputs to the differential amplifier 48 will be primarily determined by the voltage drop across the PD load RPD and will be an expected value. The value of V _se nse is then compared to a threshold value, in the manner shown in Fig. 1 , and no fault signal will be asserted. However, if there is substantial leakage current through the resistance Ri _eak> the first current loop will draw a leakage current, and the voltage difference at the inputs of the differential amplifier 48 will cause V _se nse to be greater than the threshold value to cause a fault signal to be asserted.

After a successful fault test and the handshaking routine, the power switches 21 and 22 are closed to supply the full VPSE to the PD load RPD- A different approach for sensing leakage paths in shunt with the PoDL wire pair

18 is required for the case where the PSE power switches 21 and 22 are closed and the link is already powered.

Fig. 6 illustrates a PoDL circuit where the source and return PSE currents are simultaneously sensed, differenced, and compared against an acceptable difference in order to detect a ground isolation fault while the link is powered. The power switches are not shown since they are closed. The PD load RPD is being powered by the voltage source 20. The fault detection circuit is always operating.

Low value sense resistors RSNSI and RSNS2 of equal value are in series with the source and return current paths. During normal operation, the PD load currents through both sense resistors are approximately equal if there is no ground isolation leakage. The voltage drops across the sense resistors are amplified by the differential amplifiers 50 and 52. If the source and return currents are equal, the outputs of the differential amplifiers 50 and 52 will be equal. The outputs of the differential amplifiers 50 and 52 are subtracted by a subtracter 54 to generate a signal representing the difference between the source current and return current. The output of the subtracter 54 is compared, via hysteresis comparators 56 and 58, to a high reference voltage refhi and a low reference voltage reflo, which represent an acceptable range of the difference. If the diffeence is within the acceptable range, both comparators 56/58 will output a logical zero, and there will be no fault issued. The comparators 56/58 may be referred to as a window comparator.

If there is a significant ground isolation leakage current, the return current through the sense resistor RSNS2 will be less than the source current through the sense resistor RSNSI, so the output of the differential amplifier 52 will be lower than the output of the differential amplifier 50. As a result, the output of the subtracter 54 may be higher than refhi, causing the comparator 56 to output a logical one. The OR gate 60 then asserts the fault signal. A fault signal is also asserted if the output of the subtracter 54 is below the level reflo due to a leakage path in shunt with the positive conductor of the wire pair.

A similar detection circuit may be used by reversing the inverting and non- inverting inputs of one of the differential amplifiers 50 and 52 and using a summer instead of a subtracter to detect the difference between the source current and return current.

Various other circuits and schemes may be used that are related to the embodiments described above.

While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications.