FIELD OF INVENTION

The present invention generally relates to modular multilevel converters. More particularly the present invention relates to a modular multilevel converter cell and a modular multilevel converter comprising such a cell. BACKGROUND

Multilevel converters are of interest to use in a number of different power transmission environments. They may for instance be used as voltage source converters in direct current power transmission systems such as high voltage direct current (HVDC) and alternating current power transmission systems, such as flexible alternating current transmission system (FACTS). They may also be used as reactive compensation circuits such as Static VAR compensators. The modular multilevel converter is typically made up of a number of cells, where each cell provides at least one voltage contribution that may be used for forming a waveshape.

A modular multilevel cell is typically made up of a branch of switching units in parallel with an energy storage element, where a switching unit is typically a semiconductor switching element with a parallel unidirectional conduction element. An energy storage element is in turn typically a capacitor. A semiconductor switching element may be a transistor like an Insulated Gate Bipolar Transistor (IGBT) or an Integrated Gate

Commutated Thyristor (IGCT). Furthermore, in a cell, the switching units of a branch are typically alternatingly operated so that when one of them is turned on, the other is turned off. Moreover, in such operation it is possible that one semiconductor switching element fails into short-circuit, typically because of overcurrent or overvoltage. If such a fault is in the process of occurring in a semiconductor switching element that is in a blocking state, rapidly increasing current levels may occur. The time derivative of the current is thus high. The current may rise so rapidly that the problem may be hard to handle. It is thereby of interest to handle such a fault situation in a faster way.

One technique that exists in identifying the time derivative of a fault current in an arm comprising a number of series-connected power semiconductor switches is described in WO 2004/077076. In this document a generated magnetic field of the arm is detected using a coil coupled to a rail connection of the arm. A voltage corresponding to the current derivative is then generated based on the magnetic field and used to indicate a short-circuit in the arm. The same type of technique is used in US 2015/0364909 in order to detect a short-circuit of a power switch among a number of series-connected power switches and to turn off a switch experiencing a high current time derivative. However, if this type of operation is performed for a switch in for instance the phase arm of a voltage source converter, such as an n-level voltage source converter like a two-level voltage source converter, it seems as an individually blocked switch would break down and the short-circuit current therefore still run through the power switch after a blocking.

There is in view of what has been described above of interest to obtain a fast detection of a high current time derivative in a semiconductor switching element in a cell, which can be used for handling the cell with the semiconductor switching element experiencing the high current time derivative while at the same time leaving the other cells uninfluenced. There is therefore still room for improvement with regard to such converters and then especially with regard to semiconducting switching elements experiencing high levels of the current time derivatives.

SUMMARY OF THE INVENTION

The present invention is directed towards providing a fast detection of a high time derivative of the current through a switching unit in a cell.

This object is according to a first aspect achieved through a multilevel converter cell for providing at least one voltage contribution for assisting in the conversion between Alternating Current, AC, and Direct Current, DC, the cell comprising

at least one energy storage element;

a first branch of series-connected switching units in parallel with the energy storage element, the first branch comprising a first and a second switching unit, each comprising a semiconductor switching element;

a number of gate units, each configured to actuate a corresponding switching unit;

two connection terminals for connecting the cell (HBA) in a piece of power electronics equipment,

a bypass switch connected between the two cell connection terminals; and at least one fault detection block,

wherein the gate units each comprise at least one detection loop for providing a voltage induced by a magnetic flux caused by a current running in the first branch and a corresponding fault detection block is configured to detect the voltage of a detection loop exceeding a threshold level corresponding to an excessive time derivative of the current and to actuate the bypass switch (BPS) based on said detecting. This object is according to a second aspect achieved through a multilevel converter converting between Alternating Current, AC, and Direct Current, DC, and comprising

at least one first cell, the cell comprising:

at least one energy storage element;

a first branch of series-connected switching units in parallel with the energy storage element, said first branch comprising a first and a second switching unit, each switching unit comprising a semiconductor switching element; a number of gate units, each configured to actuate a corresponding switching unit;

two connection terminals for connecting the cell (HBi) in the converter; and

a bypass switch connected between the two cell connection terminals;

wherein

the gate units each comprise at least one detection loop for providing a voltage induced by a magnetic flux caused by a current running in the first branch; and

the converter further comprising at least one fault detection block configured to detect the voltage of a detection loop exceeding a threshold level corresponding to an excessive time derivative of the current and to actuate the bypass switch based on the detecting. The invention has a number of advantages. The handling of current time derivative faults is fast. Thereby more severe problems may be avoided. As fault handling is performed for a faulty cell, it is also clear that the operation of the converter may be continued using the other healthy cells. BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will in the following be described with reference being made to the accompanying drawings, where fig. l schematically shows a cell-based voltage source converter connected between a pole and ground,

fig. 2 schematically shows a half-bridge cell,

fig. 3 schematically shows a fault detection circuit comprising a detection loop and a fault detection block and connected to gate control

functionality,

fig. 4 schematically shows three half-bridge cells where one of the half- bridge cells has a raised magnetic field caused by a short-circuit current, fig. 5 schematically shows a half-bridge cell with a clamping circuit, and fig. 6 schematically shows a detection loop connected to a gate turn off transistor and semiconductor switching element of a switching unit.

DETAILED DESCRIPTION OF THE INVENTION

In the following, a detailed description of preferred embodiments of the invention will be given.

Fig. l shows one variation of a multilevel converter in the form of a cell based voltage source converter (VSC) 10 or modular multilevel converter (MMC). The converterio operates to convert between alternating current (AC) and direct current (DC). The converter 10 in fig. l comprises a three- phase bridge made up of a number of phase legs. There are in this case three phase legs. It should however be realized that as an alternative there may be for instance only two phase legs. There is thus a first phase leg PLi, a second phase leg PL2 and a third phase leg PL3. The phase legs are more particularly connected between a first DC terminal DCi and a second DC terminal DC2, where the first DC terminal may be connected to a first pole Pi of a DC power transmission system, such as a High Voltage Direct Current (HVDC) power transmission system and the second DC terminal

DC2 may be connected to ground, where the mid points of the phase legs are connected to corresponding alternating current terminals ACAi, ACBi, ACCi. A phase leg is in this example divided into two halves, a first upper half and a second lower half, where such a half is also termed a phase arm.

The first DC pole Pi furthermore has a first potential Udp that may be positive. The first pole Pi may therefore also be termed a positive pole. The AC terminals ACAl, ACBi, ACCi may in turn be connected to an AC system, such as a flexible alternating current transmission system

(FACTS), for instance via a transformer. A phase arm between the first pole Pi and a first AC terminal ACAl, ACBi and ACCi may be termed a first phase arm or an upper phase arm, while a phase arm between the first AC terminal ACAl and ground may be termed a second phase arm or a lower phase arm.

As mentioned above, the type of voltage source converter shown in fig. l is only one example of a modular multilevel converter or a piece of power electronics equipment where the invention may be used. It is for instance possible to use the converter as a reactive compensating device, such as a Static VAR Compensator. The voltage source converter 10 depicted in fig. ι has an asymmetric monopole configuration. It is thus connected between a pole and ground. As an alternative it may be connected in a symmetric monopole

configuration or a symmetric bipole configuration. In a symmetric monopole configuration the second DC terminal DC2 would be connected to a second pole having a second negative potential that may be as large as the first potential but with the opposite polarity. In a symmetric bipole configuration there would also be a second pole. In the bipole

configuration there would furthermore be a third and a fourth phase arm in the phase leg, where the second and third phase arms would be connected to ground, the first phase arm connected between the positive voltage of the first pole Pi and the second phase arm and the fourth phase arm connected between the negative voltage of the second pole and the third phase arm. A first AC terminal of a phase leg would in the symmetric bipole configuration be provided between the first and second phase arms, while a second AC terminal of the same phase leg would be provided between the third and fourth phase arms. The phase arms are furthermore connected to the AC terminals via phase reactors.

The phase arms of the voltage source converter 10 in the example in fig. ι comprise cells. A cell is a unit that may be switched for providing a contribution to the voltage on the corresponding AC terminal. A cell then comprises one or more energy storage elements, for instance in the form of capacitors, and the cell may be switched to provide a voltage contribution corresponding to the voltage of the energy storage element or a zero voltage contribution. In this case the cell inserts the voltage of the energy storage element. If more than one energy storage element is included in a cell it is possible with even further voltage contributions. When no voltage or a zero voltage is provided by the cell then the energy storage element is bypassed.

The cells are with advantage connected in series or in cascade in a phase arm.

In the example given in fig. ι there are five series-connected or cascaded cells in each phase arm. Thus the upper phase arm of the first phase leg PLi includes five cells Cipi, C2pi, C3pi, C4pi and Cspi, while the lower phase arm of the first phase leg PLi includes five cells Cini, C2ni, C3ni, C4ni and Csni. Across the cells of the upper phase arm there is a first phase arm voltage Uvppa and through the upper phase arm there runs a first phase arm current Ivppa. As the upper phase arm is connected to the first pole Pi it may also be considered to be a positive phase arm. Across the cells of the lower phase arm there is a second phase arm voltage Uvpna and through the lower phase arm there runs a second phase arm current

Ivpna. The upper phase arm is furthermore joined to the AC terminal ACAi via a first or upper arm reactor Laarmi, while the lower phase arm is joined to the same AC terminal ACAi via a second or lower arm reactor Laarm2. In a similar fashion the upper phase arm of the second phase leg PL2 includes five cells Cip2, C2p2, C3p2, C4p2 and Csp2 while the lower phase arm of the second phase leg PL2 includes five cells Cm2, C2n2, C3n2, C4n2 and Csn2. Finally the upper phase arm of the third phase leg PL3 includes five cells Cip3, C2p3, C3P3, C4P3 and Csp3 while the lower phase arm of the third phase leg PL3 includes five cells Cm3, C2n3, C3n3, C4n3 and Csn3. The upper phase arms are furthermore joined to the corresponding AC terminals ACBi and ACCi via corresponding first or upper arm reactors Lbarmi and Lcarmi, respectively, while the lower phase arms are joined to the same AC terminal ACBi and ACCi via corresponding second or lower arm reactors Lbarm2 and Lcarm2, respectively.

The number of cells provided in fig. 1 is only an example. It therefore has to be stressed that the number of cells in a phase arm may vary. It is often favorable to have many more cells in each phase arm, especially in HVDC applications. A phase arm may for instance comprise hundreds of cells. There may however also be fewer. Control of each cell in a phase arm is normally done through providing the cell with a control signal directed towards controlling the contribution of that cell to meeting a reference voltage. The reference voltage may be provided for obtaining an AC waveform on the AC terminal of a phase leg, for instance a sine wave. In order to control the cells there is therefore a control unit 12.

The control unit 12 is provided for controlling all the phase arms of the converter. However, in order to simplify the figure only the control of the upper phase arm of the first phase leg PL is indicated in fig. 1. The control unit may be implemented through a computer.

The other phase arms are controlled in a similar manner in order to form output waveforms on the three AC terminals ACi, AC2 and AC3. There are a number of different cell types that can be used in the converter, such as full-bridge cells, double cells, and half-bridge cells. Fig. 2 shows one version of a half-bridge cell.

The cell HBA in fig. 2 is thus a half-bridge converter cell and includes an energy storage element, here in the form of a capacitor C, which is connected in parallel with a first group of switching units Si and S2. The energy storage element C provides a voltage Udm, and therefore has a positive and negative end, where the positive end has a higher potential than the negative end. The switching units Si and S2 in the first group are connected in series with each other in a first branch, which first branch is connected in parallel with the energy storage element C, where each switching unit or power switch may be realized using a first type of semiconducting element that is a unidirectional conduction element, such as a diode, and a second type of semiconducting element in the form of a switching element, such as a transistor like an IGBT (Insulated Gate Bipolar Transistor) or an IGCT (Integrated Gate Commutated Thyristor). However, also other types of semiconductor switching elements are also contemplated. The diode may be anti-parallel to the transistor. In fig. 2 the first switching unit Si has a first transistor Ti with a first anti-parallel diode Di. The first diode Di is connected between the emitter and collector of the transistor Ti and has a direction of conductivity from the emitter to the collector as well as towards the positive end of the energy storage element C. The second switching unit S2 has a second transistor T2 with a second anti-parallel diode D2. The second diode D2 is connected in the same way in relation to the energy storage element C as the first diode Di, i.e. conducts current towards the positive end of the energy storage element C. The first switching unit Si is furthermore connected to the positive end of the energy storage element C, while the second switching unit S2 is connected to the negative end of the energy storage element C. There is also a first cell connection terminal TEHBAi and a second cell connection terminal TEHBA2, each providing a connection for the cell to a phase arm of the phase leg of the voltage source converter. In this example of half-bridge cell the first cell connection terminal TEHBAi provides a connection to the junction between the first switching unit Si and the capacitor C, while the second cell connection terminal TEHBA2 provides a connection to the junction between the first and the second switching units Si and S2. These cell connection terminals thus provide points where the cell can be connected to a phase arm. Furthermore, between the two cell connection terminals TEHBAi and TEHBA2 there is a bypass switch BPS, which may be a semiconductor switch, such as a thyristor switch or a transistor switch, or even a mechanical switch. The bypass switch BPS may also have a lower on-state resistance than the first transistor Ti. It should be realized that fig. 2 shows a first type of half-bridge cell. A second type of half-bridge cell has the first cell connection terminal connected to the junction between the second switching unit S2 and the capacitor C. There is furthermore a gate unit provided for each switching unit.

Moreover, each gate unit is configured to actuate a corresponding switching unit. There is thus a first gate unit GiA and a second gate unit G2A. A gate unit provides a gate control signal of sufficient power that can be used to turn on a semiconductor switching element based on a control signal obtained from the converter control unit 12. Therefore the first gate unit GiA is connected to the gate of the first transistor Ti and the second gate unit G2A is connected to the gate of the second transistor T2. Each gate unit Gia and G2A comprises a fault detecting circuit for detecting a time derivative of the current through the corresponding power switch. A high time derivate of the current is an indication that the power switch is about to be short-circuited. In order to act on this, the fault detecting circuit can turn off the corresponding switching unit. It may also be able to bypass the cell. For this reason each gate unit can also be used to influence the bypass switch BPS, which is shown through dashed arrows going from the respective gate units GiA and G2A to the bypass switch BPS. Both the gate units are furthermore shielded against electric fields. However, they are not shielded against magnetic fields. Thereby the fault detection circuit is suitably placed in there as well, to remove any capacitive charging of the closed loop, which could give false short circuit indications.

Fig. 3 schematically shows the fault detection circuit DETiA of the first gate unit connected to gate control functionality GC 15 of the same gate unit. The fault detection circuit DETiA comprises at least one detection loop L 16 connected to a fault detection block FDB 14. The one or more loops 16 comprises at least one turn of electrical conductor. Furthermore, the one or more loops may be provided as conductive traces on one or more layers of a circuit board used in one gate unit. If there is more than one loop these are aligned with each other in a z direction, which is the normal of the plane of the circuit board, i.e. perpendicular to the circuit board. The closed loop 16 could thus be made by the conducting layer of a circuit board. More particularly it could be part of the existing gate unit board, minimizing or possibly removing the need for additional space and material.

The fault detection block 14 may be realized as hardware such as through an ASIC (Application Specific Integrated Circuit) or FPGA (Field

Programmable Gate Array) or various logic circuit combinations, for instance combinations involving a comparator. It is also possible with various passive component realizations. The fault detection block 14 may also be realized through a processor running corresponding software of a program memory. The fault detection block 14 may more particularly comprise functionality for detecting a voltage of the loop exceeding a threshold level and to, based on the detecting of the threshold level being exceeded, actuate the bypass switch BPS with a control signal BPS_CTRL and possibly also the switching unit via the gate control functionality 15. The actuating of the bypass switch may in this case involve closing the bypass switch and the actuating of a switching unit would in this case involve blocking a switching unit of the first branch associated with the detection loop. Furthermore, the threshold level would represent or correspond to an excessive time derivative of the current through a switching unit, which is an indication that the switching unit is about to be short-circuited. In case the fault detection block 14 detects a high time derivative of the current in the above-described way, this may also be reported via a signal FAULT_REP to the converter control unit 12 so that the cell is no longer used in the waveforming. As the fault detection circuit DETiA is provided in a gate unit, it may also have access to a control signal that is sufficiently powerful for actuating the bypass switch.

As mentioned earlier, the invention is concerned with acting on high time derivatives of the current through the switching units of the cells.

In operation the switching units are alternatingly operated. That is, when one switching unit of a first branch is turned on the other is turned-off or blocked. This will in turn lead to that either the voltage of the cell is inserted into the phase arm or the cell is bypassed.

In VSC applications, specifically in MMCs, the behavior of short circuit faults inside a cell can differ, depending on what state the cell was in at the moment the fault occurred. Some faults have a so called "controlled" current ramp up, e.g. when one of the switching units in the cell is conducting and fails into a short circuit, whereupon the other switch in that cell turns on. This turn-on is controlled by the driving of the healthy switching unit.

If however the conducting switching unit is not the switching unit that fails into a short circuit, but rather the blocking switching unit that fails into a short circuit, the time derivative of the current (di/dt) will be limited by the loop inductance of the commutation loop. This loop inductance might be very small, resulting in a very high di/dt, which is a current time derivative fault or a di/dt fault. If the short circuit detection and protection is too slow, this fault is not possible to handle, as the current rises too high before any protective action has had time to complete. The conventional way to solve this problem is to minimize the risk of the fault happening, while mechanically building the cell strong enough to contain the violent failure within the cell, when it happens.

The fault detection circuit DETiA is provided in order to solve this problem. The fault detection circuit DETiA works by measuring induced voltage in the closed loop 16. The induced voltage in the closed loop is proportional to the time derivative of the magnetic flux that penetrates the closed loop. The magnetic flux from a current is directly proportional to the magnitude of the current. A short circuit current is a damped sine- wave, consequently the induced voltage will be a damped cosine-wave. This means that, at the moment the short circuit starts, the induced voltage jumps up to its maximum value and this voltage may be detected for instance through detecting that the induced voltage exceeds a threshold level. It can thereby be seen that each gate unit of the cell HBA comprises at least one detection loop 16 for providing a voltage induced by a magnetic flux caused by a current running in the first branch.

The detection is "semi-instant", as the magnetic field first needs to propagate from the current through the closed loop, and then the induced voltage needs to accumulate over the fault detection block.

As the closed loop is placed inside a gate unit, it is placed in an

environment where the only thing that induces voltages over the threshold level are from the high di/dt faults in the same cell. In this case it is possible to use a passive short circuit protection; as soon as the voltage in the closed loop goes higher than the threshold level, the switching unit is turned off. Through the use of gate unit that this shielded against electric fields, it is also possible to remove any capacitive charging of the closed loop, which could give false short circuit indications.

This situation is schematically shown in fig. 4. In fig. 4 there is a first cell HBA of the described type with an energy storage element and a first and second switching unit, where the transistor gate of the first switching unit is connected to a first gate unit GiA comprising a first fault detection circuit DETiA and the transistor gate of the second switching unit is connected to a second gate unit G2A comprising a second fault detection circuit DET2A. To the left of the first cell HBA there is furthermore a second cell HBB with an energy storage element and a first and second switching unit, where a transistor gate of the first switching unit is connected to a first gate unit GiB comprising a first fault detection circuit DETiB and a transistor gate of the second switching unit is connected to a second gate unit G2B comprising a second fault detection circuit DET2B. There is also a third cell HBC on the right side of the first cell HBA, which third cell HBC also has an energy storage element and a first and second switching unit, where a transistor gate of the first switching unit is connected to a first gate unit GiC comprising a first fault detection circuit DETiC and a transistor gate of the second switching unit is connected to a second gate unit G2C comprising a second fault detection circuit DET2C. There are thus more cells connected on each side of the first cell HBA, the gate units of which comprise other detection loops. When there is a di/dt fault in for instance the first transistor Ti of the first switching unit Si of the first cell HBA, then a magnetic field is generated, which decays with distance. This field is in fig 4 shown as circles comprising crosses and dots indicating the direction of the magnetic field into and out of the plane of the paper. It can be seen that the middle cell HBA has a high di/dt fault, generating a B-field, while the cells HBB and

HBC to the left and right do not. The B-field decays with distance as 1 / distance, such that the short circuit detection in nearby cells HBB and HBC might be far enough to not trigger by the magnetic field of the failing cell. The second and third cells are thus provided at distances from the first branch of the first cell such that the current of the first cell is unable to generate a voltage in the other detection loops exceeding their

corresponding threshold levels.

The threshold voltage level of the fault detection circuit may thereby be set high enough for safely detecting a faulty switching unit in the cell, but low enough not to indicate a fault if a neighboring cell comprises a faulty switching unit. The threshold level is of course also set higher than the levels obtained at steady state operation of the cell. Thereby the fault detection circuit DETi of the first gate unit GiA in the first cell HBA may detect a di/dt fault through the loop voltage exceeding a voltage threshold and activate the bypass switch BPS based on the detection, where activation may involve closing the bypass switch BPS so that it becomes conducting. The fault detection circuit may furthermore block the faulty switching unit. It may thus block the first switching unit.

However, the gate control units of the neighboring cells will not be able to detect the fault because the magnetic field is too weak to generate a voltage exceeding the threshold level at the location of the gate units of these cells.

Furthermore, it is possible that the fault detection circuit in the gate unit connected to the healthy switching unit of the cell HBA also detects the di/dt fault. It would then also act on the fault through actuating the bypass switch and turning off the own switching unit. However, even though the turning off or blocking the own switching unit is not strictly necessary, it is still in line with common protective measures.

It can thereby be seen that the di/dt fault is detected fast and the cell with the faulty switching unit is bypassed. This improves the safety while at the same time ensuring that operation may be possible to continue with the remaining healthy cells, which are unaffected. Fig. 5 shows a clamping circuit 18 of the cell that may be used together with the fault detection circuit. The clamping circuit 18 comprises a first string in parallel with the first branch of switching units, each comprising a transistor Ti and T2, where the first string comprises a diode Dc in series with a capacitor Cc. Furthermore, there is also a second string stretching between the energy storage element C of the cell and a junction between the diode Dc and capacitor Cc of the first string, where the second string comprises a resistor Rc. The diode Dc is connected with its anode to the transistor Ti of the first switching unit and with its cathode to the capacitor Cc. The resistor Rc is connected between said junction between Dc and Cc and the positive end of the energy storage element C.

Furthermore, the first string, and thereby also the diode, is with advantage connected closer to the first branch of switching units than it is to the energy storage element C. More particularly, the diode Dc is connected closer to the first switching unit than it is to the positive end of the energy storage element C. There is a stray inductance Lstray of the cell between the positive end of the energy storage element C and the first switching unit. The placing of the string leads to there being a division of the stray inductance Lstray of the cell so that a first part Lstrayi that appears between the energy storage element C and the diode Da is significantly higher than a second part L _s tray2 that appears between the diode Da and the first transistor Ti.

The clamping circuit has the advantage of reducing the overvoltage instead of requiring a "soft turn on". This feature further increases the speed of the fault detection.

It is possible to use a simplified turn off of a faulty switching unit. One way in which this may be realized is shown in fig. 6, where the detection loop 16 is connected to the gate of a gate turn-off transistor 20, which is a transistor used to turn off the transistor Ti of the faulty switching unit. The gate turn off transistor is in this case a MOSFET (Metal Oxide

Semiconductor Field Effect Transistor), the source of which is connected to a gate turn off potential, which is exemplified by - 5 V, and the drain of which is connected to the gate of the transistor Ti in the faulty switching unit, which transistor in this case is an IGBT. The gate of the gate turn-off transistor is thus connected to the detection loop and the other transistor terminals connect the transistor 20 between the gate of the semiconductor of turn off type and a gate turn-off potential. The MOSFET gate may here be set to turn on at the threshold level. Thereby the detection of current derivatives through a loop voltage exceeding the threshold level, will turn on the gate turn off transistor 20, which in turn will block the faulty cell transistor Ti. The gate turn off transistor 20 is in this way set to conduct at the threshold voltage thereby turning off the semiconductor switching element in the case of a di/dt fault. The exceeding of the voltage may, as was mentioned earlier, also be used for controlling the bypass switch. Some more functionality could be added by e.g. adding a LED (Light

Emitting Diode) that can give the cell electronics information that a di/dt fault has been found and the switching unit has been turned off, such that the control can regulate the standard driving to also turn-off. A current limiting resistor can possibly be added between transistors Ti and 20, to slow down the turn-off. Possibly a diode could be added at the gate of the

MOSFET, to keep it on after being activated, such that the IGBT is kept off.

It should be realized that it is possible to perform further variations in addition to those already described.

For instance, the invention has been described in relation to a half-bridge cell. It should be realized that it is not limited to this cell, but may be used in relation to any type of cell, such as in relation to full-bridge cells, where there is a second branch of switching units in parallel with the first branch of switching units. In this case the detection of a faulty switching unit in any branch connected in parallel with an energy storage element may be used to bypass the cell as well as to block the switching unit in question. In the example given above there was one fault detection block per switching unit, each provided in a corresponding gate unit. However, the fault detection block need not be provided in a gate unit. It may be provided in a separate unit that receives the loop voltage. The fault detection block may as one example be provided as a separate unit. It may as another example be provided in the control unit. It is also possible that there is only one fault detection block provided for a cell.

Furthermore, the transistor of a cell is not limited to an IGBT. It may for instance be an Junction Field Effect Transistor (JFET) or a SiC Metal- Oxide-Semiconductor Field-Effect Transistor (MOSFET) instead. The semiconductor switching element is not limited to a transistor. It may for instance also be an Integrated Gate-Commutated Thyristor (IGCT). From the foregoing discussion it is evident that the present invention can be varied in a multitude of ways. It shall consequently be realized that the present invention is only to be limited by the following claims.