TECHNICAL FIELD

[0001] In some example embodiments, the subject matter herein generally relates to wireless communications and a boot sequence for in a MIMO radios of the wireless communication system.

BACKGROUND

[0002] In digital wireless communications systems like cellular communications implementing Long Term Evolution (LTE) and fifth generation (5G) New Radio (NR), Multiple-Input-Multiple-Output (MIMO) radios are a standard radio configuration.

[0003] A MIMO radio board or radio card may typically include sixteen (16) transmit and receive circuits/elements. MIMO radio boards with 16 transmit and receive circuits are fairly large and are densely populated. As demand for wireless access continues to grow, the need for 32, 64, 96, and even 128 element radios may be necessary. Thus, multiple MIMO radio boards or radio cards may need to be chained together to achieve 32 element, 64, element and larger radios to meet network requirements. An corresponding antenna array (not shown) may match the number of transmit/receive elements.

[0004] Each MIMO radio board or radio card may include a Field Programmable Gate Array (FPGA). In a wireless network, multiple MIMO radio boards may be connected to a centralized hub for operational purposes. That is, a centralized hub may provide operational control of the boot sequence of MIMO radio cards that are linked or chained together. In addition to providing operational control of the boot sequence, the centralized hub provides operational control to update the firmware in the MIMO radio cards.

[0005] As radio boards are added or chained together to meet network requirements, the number of connections between the FPGAs and radios of the corresponding MIMO radio board increases, and the limited number of pins or connections in the FPGAs and/or radios may limit the number of MIMO radio boards that may be chained together.

[0006] As network MIMO radios are increased to 32, 64, and 128 element radios, the number of additional connections may increase the operational maintenance of the respective MIMO radio units, and the limited number of connection pins may limit the ability to chain together multiple MIMO radio boards.

[0007] In view of at least the foregoing, the need exists for an efficient and flexible techniques to chain multiple MIMO radio boards together and ease operational control and maintenance.

SUMMARY

[0008] In one general aspect, A Multiple Input Multiple Output (MIMO) radio card booting system may include a plurality of MIMO radio boards where each of the plurality of MIMO radio boards includes an Field Programmable Gate Array (FPGA), and where each of the plurality of MIMO radio boards are connected via their respective FPGA. The MIMO radio card booting system may also include a hub configured to: communicate with at least a first FPGA of a first MIMO radio board among the plurality of MIMO radio boards, initialize a boot sequence in the first FPGA of the first MIMO radio board, and control the first FPGA of the first MIMO radio board to initialize the boot sequence in at least a second FPGA of a second MIMO radio board among the plurality of MIMO radio boards, the first and second MIMO radio boards connected via the first and second FPGA respectively. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0009] Embodiments may include one or more of the following features. The MIMO radio board booting system where the plurality of MIMO radio boards are connected in series via the FPGA of the corresponding MIMO radio board. The MIMO radio board booting system where each of the plurality of radio boards is connected to its corresponding FPGA via an ethernet signal, an Universal Asynchronous Receiver/Transmitter (UART) signal, and at least one control signal. The MIMO radio board booting system where each of the FPGAs corresponding to its respective MIMO radio boards is configured to receive one of the at least one control signal at one General- Purpose Input/Output (GPIO) pin and receive another of the at least one control signal at another GPIO pin either alone or in combination when two control signals are received, where one GPIO pin is a reset pin and another GPIO pin is a boot mode select pin. The MIMO radio board booting system where the first FPGA of the first MIMO radio board is a primary FPGA and the second FPGA of the second MIMO radio board is a secondary FPGA. The MIMO radio board booting system where the secondary FPGA of the second MIMO radio board is connected to a primary FPGA of a third MIMO radio board, and the primary FPGA of the third MIMO radio board is connected to a secondary FPGA of a fourth MIMO radio board. The MIMO radio board booting system where the secondary FPGA of the second MIMO radio board is connected to the primary FPGA of the third MIMO radio board via bidirectional communication lines where the bidirectional communication lines include at least one of an UART communication line and an ethernet communication line, the bidirectional communication lines including control information. The MIMO radio board booting system where the hub is connected to the first FPGA of the first radio board via an ethernet pin, an Universal Asynchronous Receiver/Transmitter (UART) pin, and at least one control pin or via bidirectional communication lines include at least one of an UART communication line and an ethernet communication line, the bidirectional communication lines including control information. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium

[0010] In another general aspect, an apparatus for booting MIMO radio boards or radio cards may include a plurality of MIMO radio boards where each of the plurality of MIMO radio boards includes an Field Programmable Gate Array (FPGA). The apparatus for booting MIMO radio boards may also include a hub configured to: communicate with at least a first FPGA of a first MIMO radio board among the plurality of MIMO radio boards and at least a second FPGA of a second MIMO radio board of the plurality of radio boards; initialize a boot sequence in the first FPGA of the first MIMO radio board; and initialize a boot sequence in the second FPGA of a second MIMO radio board. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0011] Embodiments may include one or more of the following features. The apparatus for booting MIMO radio boards where the hub is further configured to: communicate with at least a third FPGA of a third MIMO radio board among the plurality of MIMO radio boards and a fourth FPGA of a fourth MIMO radio board of the plurality of radio boards, initialize a boot sequence in the third FPGA of the third MIMO radio board, and initialize a boot sequence in the fourth FPGA of the fourth MIMO radio board. The apparatus for booting Ml MO radio boards where the hub is further configured to control the first FPGA of the first MIMO radio board to initialize the boot sequence of a third FPGA of a third MIMO radio board connected in series with the first MIMO radio board and control the second FPGA of the second MIMO radio board to initialize the boot sequence of a forth FPGA of a forth MIMO radio board connected in series with the second MIMO radio board. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium

[0012] In one yet another general aspect, a method may include communicating with at least a first Field Programmable Gate Array (FPGA) of a first MIMO radio board among a plurality of MIMO radio boards by a hub. The method may also include initializing a boot sequence in the first FPGA of the first MIMO radio board by the hub.

[0013] The method may furthermore include controlling by the hub the first FPGA of the first MIMO radio board to initialize the boot sequence in at least a second FPGA of a second MIMO radio board among the plurality of MIMO radio boards, the first and second MIMO radio boards connected via a first FPGA and second FPGA respectively.

[0014] Embodiments may include one or more of the following features. The method where the plurality of MIMO radio boards are connected in series via the FPGA of the corresponding MIMO radio board. The method may include connecting each of the plurality of radio boards is to its corresponding FPGA via an ethernet signal, an Universal Asynchronous Receiver/Transmitter (UART) signal, and at least one control signal. The method where each of the FPGAs corresponding to its respective MIMO radio boards is configured to receive one of the at least one control signal at one General-Purpose Input/Output (GPIO) pin and receive another of the at least one control signal at another GPIO pin either alone or in combination when two control signals are received, where one GPIO pin is a reset pin and another GPIO pin is a boot mode select pin.

[0015] The method where the first FPGA of the first MIMO radio board is a primary FPGA and the second FPGA of the second MIMO radio board is a secondary FPGA. The method may include connecting the secondary FPGA of the second MIMO radio board is to a primary FPGA of a third MIMO radio board, and connection the primary FPGA of the third MIMO radio board to a secondary FPGA of a fourth MIMO radio board. The method where the secondary FPGA of the second MIMO radio board is connected to the primary FPGA of the third MIMO radio board via bidirectional communication lines where the bidirectional communication lines include at least one of an UART communication line and an ethernet communication line, the bidirectional communication lines including control information. The method where the hub is connected to the first FPGA of the first radio board via an ethernet pin, an Universal Asynchronous Receiver/Transmitter (UART) pin, and at least one control pin or via bidirectional communication lines include at least one of an UART communication line and an ethernet communication line, the bidirectional communication lines including at least one control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the following drawings:

[0017] Fig. 1 is a diagram of a hub and MIMO radio boards according to an embodiment;

[0018] Fig. 2 is a diagram of MIMO radio boards according to an embodiment;

[0019] Fig. 3 is a diagram of a hub and MIMO radio boards according to embodiments; and

[0020] Fig. 4 is flowchart representing a process of booting MIMO radio boards according to an embodiment.

DETAILED DESCRIPTION

[0021] Fig. 1 illustrates a hub and MIMO radio boards. As shown in Fig. 1 , the hub 102 is connected to two FPGA 104 MIMO radio boards or radio cards, 106A, and 106B. MIMO radio boards 106A and 106B are configured the same and are essentially identical but different MIMO radio boards. Generally, the difference between FPGA MIMO radio boards 106A and 106B may be the order in which they are configured. Hub 102 may include two or more ethernet pins 102 and 104 for ethernet communication, two or more programmable logic pins 110 and 114 for loading and updating firmware including a bootloader. In addition, the hub may have two or more GPIO pins where one GPIO pin is a reset pin and another GPIO pin is a boot mode select pin.

[0022] The hub 102 may be coupled with two or more MIMO radio boards. The MIMO radio boards shown in Fig. 1 include MIMO radio board 106A and MIMO radio boards 106B. MIMO radio board 106A includes ethernet connection pin 118A, uart connection pin 120A, and reset/boot mode pin 122A.

[0023] MIMO radio board 106B includes ethernet connection pin 118B, uart connection pin 120B, and reset/boot mode pin 122B. [0024] To initiate a boot sequence and to facilitate operational maintenance and control including firmware updates, the connection between radios 106A and 106B and hub 102 includes at least one control signal connected to a GPIO pin according to a reset mode or a boot mode. The reset and/or boot mode connection is indicated at 122A for MIMO radio board 106A, and 122B for MIMO radio board 106B as described above.

[0025] Fig. 2 is a diagram of a MIMO radio blocks. The four (4) blocks, each comprising two FPGAs and two MIMO radios, are shown in 202A-202D. Each of the four blocks 202A-202D may be configured the same. Elements in block 202A will be described. However, one skilled in the art should appreciate that the description of the elements in block 202A may be applied equally to corresponding elements in blocks 202B-202D.

[0026] Block 202A includes FPGA 204 corresponding to MIMO radio (R2R) 208, and FPGA 206 corresponding to MIMO radio (R2R) 210. Thus, each MIMO radio board includes a respective FPGA. Three connections between the radio (R2R) and its respective FPGA may be necessary. For example R2R 208 includes connections for a uart 220, an ethernet connection 222 and at least one GPIO pin for a reset or boot mode 224.

[0027] FPGA 204 includes uart pin 216, ethernet pin 218, and reset/boot mode pin 220 corresponding to uart 220 ethernet connection 222 and at least one GPIO pin for a reset or boot mode 224 on R2R 208. FPGA 204 may include connections to Quad Serial Peripheral Interface (QSPI) 212 for flash chip communication and Double Data Rate (DDR) memory 214. QSPI 212 and DDR 214 may be implemented to store the boot loader.

[0028] R2R 210 includes connections for a uart 226, an ethernet connection 228 and at least one GPIO pin for a reset or boot mode 230.

[0029] FPGA 206 includes uart pin 232, ethernet pin 234, and at least one of a reset/boot mode pin 236 connected to reset/boot mode pin 230 on R2R 210. FPGA 204 and FPGA 206 are connected via bidirectional communication pins. Thus, uart and ethernet pins may be used for bidirectional communication between FPGA 204 and FPGA 206. FPGA 206 may also include Quad Serial Peripheral Interface (QSPI) 238 for flash chip communication and Double Data Rate (DDR) memory 240.

[0030] In an embodiment, a hub such as hub 104 shown in Fig. 1 may be connected to FPGA 204. The hub may be connected to FPGA 204 via, uart 216, ethernet 218, and at least one reset/boot mode pin 220. In addition, the hub may be connected to FPGA 204 via high speed ethernet connection, for example 10 Gigabit Ethernet Backplane at 242.

[0031] The hub may initiate a boot sequence in FPGA 204 to boot R2R 208 via a boot loader. In addition, the hub may control FPGA to initiate the boot sequence in FPGA 206 to boot R2R 210. The communication between FGPA 204 and FGPA 206 may be via uart pin 232 and ethernet pin 234 for bidirectional communication as described above. This would be an example where FPGA 204 is a primary FPGA 206 and is a secondary FPGA. Stated another way FPGA 204 would be the controller FPGA and FPGA 206 would be the controlled FPGA. The hub may initiate the boot sequence such that the primary FPGA 204 boots R2R 208, and FPGA 204 controls initialization of the boot sequence in FPGA 206. This process may be extended to a primary FPGA in block 202B and secondary FPGA in block 202B, In addition, block 202B may be connected to block 202C etc. It can be seen the respective FGPA/MIMO radios may be connected in series.

[0032] Each FPGA has a logical connection that is independent of the physical connection. That is, there is a logical connection that is independent of where or in what order the radios are placed thus, providing flexibility in the configuration.

[0033] Block 202A illustrates a configuration of two sixteen (element) transmit/receive Ml MO radios resulting in a 32 element transmit/receive configuration.

[0034] As described above, each of the four blocks 202A-202D may be configured the same. Thus, the description of the elements in block 202A may be applied equally to blocks 202B-202D. In addition, block 202A may be chained together with another MIMO radio board (FPGA/R2R radio), and/or block 202A may be chained together with another block as such as block 202B, which may be chained to block 202C, which may be chained to block 202D and so on.

[0035] Block 202A, 202B, and 202D may be chained together in any combination. The blocks may be chained together to increase the number of transmit/receive elements and/or chained together to initiate a boot sequence in a sequential order.

[0036] In an embodiment, the blocks 202A through 202D may be configured as a 32 element transmit/receive blocks, and blocks 202A-202D may be chained together so that each MIMO radio may be booted in sequence. [0037] In addition, chaining another block, for example chaining block 202A to block 202B, may be done to increase form a 32 element transmit/receive configuration to a 64 element transmit/receive configuration.

[0038] For example, FPGA 206 may be configured to communicate with a primary FPGA in block 202B. The primary FPGA in block 202B may be connected to a secondary FPGA in block 202B. This would result in a 64 element transmit/receive configuration. If necessary, block 202B may be chained with block 202C to provide a 96 element transmit/receive configuration, and block 202D may be added to the chain to provide a 128 element transmit/receive configuration.

[0039] The above described techniques provide an efficient and flexible method to expand and manage the MIMO radio boards in a wireless communication system while overcoming the limited number of available pins.

[0040] Fig. 3 is a diagram of a hub and MIMO radio boards according to several embodiments. Fig. 3 illustrates the configuration show in Fig. 1 and the configuration shown in Fig. 2. The hub 102 may be connected to MIMO radios R2R 106A and R2R 106B. This configuration may be expanded in parallel coupling additional R2Rs with the hub 102.

[0041] In another embodiment, the configuration 100 may be expanded in series where R2R radio boards 106A and 106B may connected to the hub as illustrated in 100 and then extended in series. That is, radio 106A may be coupled with primary FPG 204, and R2R radio board 106B may be connected to a primary FPGA of block 202B. This may be performed by connecting the hub 102 FPGA 104 (pins 108, 110, and a GPIO) to FPGA 204 (pins 216, 218, and 220). That is connecting eth 108 to eth 218, connecting pluart(O) 110 to uart 216, and connecting at least one control GPIO of the hub with reset/boot mode pin 220. Radio 106B may be similarly connected to block 202B.

[0042] In yet another embodiment, the primary FPGA in block 202A may replace the hub connections to R2R 106A, and the primary FPGA in block 202B may replace the hub connections to R2R 106B. Each of Block 202A and block 202B may be expanded in series with additional MIMO radio boards or blocks, for example blocks 202C and 202D respectively.

[0043] The configuration in 100 may be expanded by adding block 202A as described above and adding block 202B to the hub 102 by connecting eth 112, pluart 114, and at least one control pin to the respective corresponding pins in the primary FPGA of block 202B. Thus, blocks 202A and 202B may be connected to hub 102 in parallel where each of blocks 202A and 202B may be expanded in series as illustrated in block 202A.

[0044] In a further embodiment, eth 106A, uart 120A, and reset/boot mode pins 122A may be connected to eth 218, uart 216 and reset/boot mode pins 220. In addition, eth 106B, uart 120B and reset/boot mode pins 122B may be connected to corresponding pins a of primary FPGA, thus allowing serial expansion.

[0045] It should be appreciated that the eth, uart, and one or more GPIO pins from the hub 102 to block 202A may be via a high speed ethernet connection 242, and block 202A may be connected to another MIMO radio board or another block via a high speed ethernet connection 244.

[0046] Fig. 4 is a flowchart representing a process of booting MIMO radio boards according to an embodiment. In some embodiments, one or more process blocks of Fig. 4 may be performed by an apparatus or a system.

[0047] As shown in Fig. 4, process 400 may include communicating with at least a first Field Programmable Gate Array (FPGA) of a first MIMO radio board among a plurality of MIMO radio boards by a hub at 402. For example, the hub may communicate with at least a first FPGA of a first MIMO radio board among a plurality of MIMO radio boards, as described above. As also shown in Fig. 4, process 300 the hub may include initializing a boot sequence in the first FPGA of the first MIMO radio board at 404. For example, a boot sequence may be initialized in the first FPGA of the first MIMO radio board at the hub, as described above. As further shown in Fig. 4, process 400 may include the hub controlling the first FPGA of the first MIMO radio board to initialize the boot sequence in at least a second FPGA of a second MIMO radio board where the first and second MIMO radio boards connected via a first FPGA and second FPGA respectively at 406. For example, the hub may control the first FPGA of the first MIMO radio board to initialize the boot sequence in at least a second FPGA of a second MIMO radio board among the plurality of MIMO radio boards, the first and second MIMO radio boards being connected via a first FPGA and second FPGA respectively, as described above. The initialization sequence may continue through each MIMO radio board sequentially.

[0048] Process 400 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein. In a first implementation, the plurality of MIMO radio boards are connected in series via the FPGA of the corresponding MIMO radio board at 408.

[0049] A second implementation, alone or in combination with the first implementation, process 400 may include connecting each of the plurality of radio boards is to its corresponding FPGA via an ethernet signal, an Universal Asynchronous Receiver/Transmitter (UART) signal, and at least one control signal at 410.

[0050] In a third implementation, alone or in combination with the first and second implementation, each of the FPGAs corresponding to its respective MIMO radio boards is configured to receive one of the at least one control signal at one or more General- Purpose Input/Output (GPIO) pins and receive another of the at least one control signal at another GPIO pin either alone or in combination when two control signals are received, where one GPIO pin is a reset pin and another GPIO pin is a boot mode select pin at 412.

[0051] In a fourth implementation, alone or in combination with one or more of the first through third implementations, the first FPGA of the first MIMO radio board is a primary FPGA and the second FPGA of the second MIMO radio board is a secondary FPGA at 414.

[0052] A fifth implementation, alone or in combination with one or more of the first through fourth implementations, process 400 may include connecting the secondary FPGA of the second MIMO radio board is to a primary FPGA of a third MIMO radio board, and connection the primary FPGA of the third MIMO radio board to a secondary FPGA of a fourth MIMO radio board at 416.

[0053] A sixth implementation, alone or in combination with one or more of the first through fourth implementations, process 400 may include connecting the secondary FPGA of the second MIMO radio board to the primary FPGA of the third MIMO radio board via bidirectional communication lines wherein the bidirectional communication lines include at least one of a UART communication line and an ethernet communication line, the bidirectional communication lines including control information at 418.

[0054] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed features, from a study of the drawings, the disclosure, and the appended claims. [0055] In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality.

[0056] A single processor, device or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0057] Operations like acquiring, accessing, analyzing, capturing, comparing, determining, displaying, inputting, obtaining, outputting, providing, store or storing, calculating, simulating, receiving, warning, and stopping can be implemented as program code means of a computer program and/or as dedicated hardware.

[0058] A computer program may be stored and/or distributed on a suitable medium, such as an optical storage medium or a solid-state medium, supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.