RESONATORS

Technical Field

[0001] This application relates generally to solidly mounted acoustic resonators, and more particularly to solidly mounted acoustic resonators that suppress spurious modes.

Background

[0002] Semiconductor integrated chips can be fabricated in a process that includes imaging, deposition and etching. Additional steps can include doping and cleaning. Wafers (such as mono-crystal silicon wafers, silicon on sapphire wafers or gallium arsenide wafers) can be used as a substrate. Photolithography can be used to mark areas of the wafer for enhancement through doping or deposition. An integrated circuit is composed of a plurality of layers which can include diffusion layers (which can include dopants), implant layers (which can include additional ions), metal layers (defining conduction) and/or via or contact layers (which can define conduction between layers).

Brief Description of the Drawings

[0003] FIG. 1 illustrates a cross-section view of a conventional acoustic resonator with a metal frame.

[0004] FIG. 2 illustrates a cross-section view of an acoustic resonator according to some embodiments of the disclosure.

[0005] FIG. 3 illustrates a top view of an acoustic resonator according to some embodiments of the disclosure.

[0006] FIG. 4 illustrates a corner top view of an acoustic resonator according to some embodiments of the disclosure.

[0007] FIG. 5 illustrates a cross-section view of an acoustic resonator according to other embodiments of the disclosure.

[0008] FIG. 6 is a flow chart for fabricating an acoustic resonator according to some embodiments of the disclosure.

[0009] FIG. 7 illustrates an interposer implementing one or more embodiments of the disclosure.

[0010] FIG. 8 illustrates a computing device built in accordance with an

embodiment of the disclosure. Detailed Description of Preferred Embodiments

[0011] Described herein are systems and methods of a solidly mounted acoustic resonator that includes a metal-mesh frame. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative

implementations.

[0012] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the embodiments. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0013] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0014] Implementations of embodiments of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one

implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the embodiments.

[0015] A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the embodiments, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the embodiments may also be carried out using nonplanar transistors.

[0016] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0017] The gate electrode layer is formed on the gate dielectric layer and may include at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may include a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0018] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0019] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions

substantially perpendicular to the top surface of the substrate. In further

implementations of the embodiments, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0020] In some implementations of the embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0021] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternative semiconductor materials such as germanium or a group lll-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0022] One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.

Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0023] Spurious resonances near the main resonance of a radio frequency (RF) acoustic resonator will show up as a ripple and/or reduced insertion loss in a bandpass of a bandpass filter and adversely affect the bandpass filter performance.

[0024] FIG. 1 illustrates a cross-section view of a conventional solidly mounted acoustic resonator 100 that reduces spurious resonances. The acoustic resonator 100 includes a bottom metal layer 102. The bottom metal layer 102 is disposed over a semiconductor mirror 1 12, which is disposed over a substrate 1 14. The

semiconductor mirror 1 12 consists of several layer pairs of high and low acoustic impedance materials. A piezoelectric layer 104 is disposed over the bottom metal layer 102. A top metal layer 106 is disposed over the piezoelectric layer 104. The bottom metal layer 102 and the top metal layer 106 include electrically conductive materials and provide an oscillating electric field in the y-direction, which is the direction of the thickness of the piezoelectric layer 104. The y-axis of the coordinate system depicted in FIG. 1 is the axis for the transverse-electric (TE) (longitudinal) modes for the resonator.

[0025] The acoustic resonator 100 includes at least one recess 108 and a frame element 1 10. The recesses 108 may be provided on one or more sides of the top metal layer 106. Similarly, the frame element 1 10 may be provided over one or more sides of the top metal layer 106.

[0026] The acoustic resonator 100 suppresses spurious modes by terminating the edges of the resonator by a specific border layer - recesses 108 and frame element 1 10. This improves the quality factor of the acoustic resonator 100 and eliminates ripples in a bandpass of a bandpass filter.

[0027] The width (w) of the recess 108 and the height (h) of the frame element 1 10 are set to selectively excite a desired TE mode.

[0028] To fabricate the acoustic resonator 100 of FIG. 1 , an extra mask must be used to create the border layer including recesses 108 and frame element 1 10. A first mask is used to deposit the top metal layer 106. Then, a second mask is used to etch out a portion of the top metal layer 106 to create recesses 108. Etching may not be accurate, resulting in a less efficient acoustic resonator.

[0029] FIG. 2 illustrates an acoustic resonator 200 according to some

embodiments of the disclosure. The acoustic resonator 200 includes a substrate 202, a semiconductor mirror 216 disposed over the substrate 202, and a bottom metal region 204 disposed over the semiconductor mirror 216. As mentioned above, the semiconductor mirror 216 consists of several layer pairs of high and low acoustic impedance materials. A piezoelectric region 206 is disposed over the bottom metal region 204 and a top metal region 208 is disposed over the piezoelectric region 206. The bottom metal region 204, piezoelectric region 206 and the top metal region 208 may be regions and/or layers disposed over the substrate.

[0030] The top metal region 208 includes an outer frame portion 210, a middle portion 212, and a metal-mesh portion 214 located between the outer frame portion 210 and the middle portion 212. Preferably, the metal-mesh portion 214 surrounds all or substantially all of the middle portion 212. The outer frame portion 210 surrounds all or substantially all of the metal-mesh portion 214. The metal-mesh portion 214 and the outer frame portion 210 may be annular or any other shape suitable to surround all or substantially all of the middle portion 212.

[0031] The bottom metal region 204 and the middle portion 212 of the top metal region 208 each include electrically conductive materials. That is, each of the bottom metal region 204 and the middle portion 212 include an electrode. The electrodes provide an oscillating electric field when applying a current to one of the electrodes in the y-direction, which is the direction of the thickness of the

piezoelectric region 206.

[0032] FIG. 3 illustrates a top-view of an acoustic resonator 300 according to some embodiments of the disclosure. As seen, the acoustic resonator 300 includes a middle portion 312 surrounded by a mesh-metal portion 314, which is further surrounded by a solid outer frame 310. In this embodiment, the middle portion 312, the metal-mesh portion 314 and the solid outer frame 310 are each rectangular. Similar to FIG. 2, the solid outer frame 310, the metal-mesh portion 314 and the middle portion 312 are each on a single region above a piezoelectric region and a second electrically conductive region (not shown). The device may be included on a substrate 302 with additional components, or as a single device on the substrate 302.

[0033] FIG. 4 illustrates a zoomed in top view of a corner portion of an acoustic resonator 400 according to some embodiments. Similar to the acoustic resonator 300, the acoustic resonator 400 includes a solid outer frame 410, a middle portion 412 and a metal-mesh portion 414 between the solid outer frame 410 and the middle portion 412. The acoustic resonator 400 is on a substrate 402. The embodiment of FIG. 4 illustrates the width L of the solid-mesh frame and the line-to-line ratio r of the metal-mesh frame. These variables are chosen based on the characteristics of the acoustic resonator 400, similar to the width w and height h of the conventional acoustic resonator of FIG. 1 . That is, the metal-mesh portion 414 of the acoustic resonator 400 will have a pre-defined width L and line-to-space ratio r to control the density and acoustic impedance. The solid outer frame 410 also has a defined width to satisfy boundary conditions to selectively excite the desired TE mode. These features apply to each of the acoustic resonators shown in FIGS. 2 and 3, as well.

[0034] In some embodiments, such as shown in FIG. 5, a top metal region 508 of an acoustic resonator 500 may be partially embedded into a piezoelectric region 506. The remaining features of the acoustic resonator are similar to those discussed above with respect to FIGS. 2-4, and as such are not discussed in further detail. That is, the acoustic resonator 500 also includes a bottom metal region 504, a substrate 502, and a semiconductor mirror 516. The top metal region 508 includes an outer frame portion 510, a middle portion 512, and a metal-mesh portion 514.

[0035] The acoustic resonators in FIGS. 2-4 may be manufactured without adding any additional masks compared to the acoustic resonator 100 by eliminating an etching step required to manufacture the acoustic resonator 100 discussed above.

[0036] FIG. 6 illustrates a method for manufacturing the acoustic resonators of FIGS. 2-4. The method includes disposing 600 a semiconductor mirror over a substrate, disposing 602 a first metal layer on the semiconductor mirror, and disposing 604 a piezoelectric layer over the first metal layer. A second metal layer is disposed 606 over the piezoelectric layer, the second metal layer including a solid outer frame portion, a middle portion, and a metal-mesh portion between the solid outer frame portion and the middle portion. Each of the first metal layer and the second metal layer is disposed using photolithography. A pre-defined metal line-to- space ratio is provided to dispose the metal-mesh of the second metal layer. As discussed previously, at least a portion of each of the first electrode, the metal-mesh portion, and the solid outer frame may be embedded in a top portion of the piezoelectric layer.

[0037] FIG. 7 illustrates an interposer 1000 that includes one or more

embodiments of the disclosure. The interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for instance, an integrated circuit die. The second substrate 1004 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004. In some

embodiments, the first and second substrates 1002, 1004 are attached to opposing sides of the interposer 1000. In other embodiments, the first and second substrates 1002, 1004 are attached to the same side of the interposer 1000. And in further embodiments, three or more substrates are interconnected by way of the interposer 1000. [0038] The interposer 1000 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer 1000 may be formed of alternative rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.

[0039] The interposer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. The interposer 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and

electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000.

[0040] In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of the interposer 1000.

[0041] FIG. 8 illustrates a computing device 1200 in accordance with one embodiment of the disclosure. The computing device 1200 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. The components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications chip 1208. In some implementations the communications logic unit 1208 is fabricated within the integrated circuit die 1202 while in other implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202. The integrated circuit die 1202 may include a processor 1204 as well as on-die memory 1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin- transfer torque memory (STT-MRAM).

[0042] The computing device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), non-volatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit (GPU) 1214, a digital signal processor (DSP) 1216, a crypto processor 1242 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, at least one antenna 1222 (in some implementations two or more antennae may be used), a display or a touchscreen display 1224, a touchscreen controller 1226, a battery 1228 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1244, a compass (not shown), a motion coprocessor or sensors 1232 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 1234, a camera 1236, user input devices 1238 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1240 (such as a hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 1200 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 1200 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 1200 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

[0043] The communications logic unit 1208 enables wireless communications for the transfer of data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1200 may include a plurality of communications logic units 1208. For instance, a first communications logic unit 1208 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth, and a second communications logic unit 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0044] The processor 1204 of the computing device 1200 includes one or more devices, such an acoustic resonator with a top metal region having a solid outer frame surrounding or substantially surrounding a metal-mesh portion that further surrounds or substantially surrounds an electrically conductive portion, that are formed in accordance with embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0045] The communications logic unit 1208 may also include one or more devices, such as such an acoustic resonator with a top metal region having a solid outer frame surrounding or substantially surrounding a metal-mesh portion that further surrounds or substantially surrounds an electrically conductive portion, that are formed in accordance with embodiments of the disclosure.

[0046] In further embodiments, another component housed within the computing device 1200 may contain one or more devices, such as an acoustic resonator with a top metal region having a solid outer frame surrounding or substantially surrounding a metal-mesh portion that further surrounds or substantially surrounds an electrically conductive portion, that are formed in accordance with implementations of the embodiments of the disclosure.

[0047] In various embodiments, the computing device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further

implementations, the computing device 1200 may be any other electronic device that processes data.

Example Embodiments

[0048] The following is a list of example embodiments that fall within the scope of the disclosure. In order to avoid complexity in providing the disclosure, not all of the examples listed below are separately and explicitly disclosed as having been contemplated herein as combinable with all of the others of the examples listed below and other embodiments disclosed hereinabove. Unless one of ordinary skill in the art would understand that these examples listed below, and the above disclosed embodiments, are not combinable, it is contemplated within the scope of the disclosure that such examples and embodiments are combinable.

[0049] Example 1 is a solidly mounted acoustic resonator. The resonator includes a first metal region on a substrate and a piezoelectric region over the first metal region. The resonator includes a second metal region over the piezoelectric region, the second metal region including an outer frame portion, a middle portion, and a metal-mesh portion between the outer frame portion and the middle portion.

[0050] Example 2 is the solidly mounted acoustic resonator of Example 1 , where the first metal region includes a first electrode and the middle portion of the second metal region includes a second electrode.

[0051] Example 3 is the solidly mounted acoustic resonator of Example 1 , where the metal-mesh portion and the outer frame portion are the same material.

[0052] Example 4 is the solidly mounted acoustic resonator of Example 1 , where the metal-mesh portion and the outer frame portion are different materials.

[0053] Example 5 is the solidly mounted acoustic resonator of Example 1 , where the metal-mesh portion and the outer frame portion are integrally formed with the middle portion.

[0054] Example 6 is the solidly mounted acoustic resonator of Example 1 , where the metal-mesh portion has a predefined metal line-to-space ratio.

[0055] Example 7 is the solidly mounted acoustic resonator of any one of

Examples 1 -6, where at least a portion of each of the metal-mesh portion, the middle portion, and the outer frame portion of the second metal region are embedded in a top portion of the piezoelectric region.

[0056] Example 8 is a bandpass filter including the solidly mounted acoustic resonator of any one of Examples 1 -6.

[0057] Example 9 is a method of fabricating a solidly mounted acoustic resonator. The method includes disposing a first metal layer on a substrate and disposing a piezoelectric layer over the first metal layer. The method includes disposing a second metal layer over the piezoelectric layer, the second metal layer including a solid outer frame portion, a middle portion, and a metal-mesh portion between the solid outer frame portion and the middle portion.

[0058] Example 10 is the method of Example 9, where the metal-mesh portion is formed via lithography.

[0059] Example 1 1 is the method of Example 9, where the first metal layer includes a first electrode and the middle portion of the second metal layer includes a second electrode.

[0060] Example 12 is the method of Example 9, where the metal-mesh portion and the solid outer frame are the same material.

[0061] Example 13 is the method of Example 9, where the metal-mesh portion and the solid outer frame are different materials.

[0062] Example 14 is the method of Example 9, where the metal-mesh portion and the solid outer frame are integrally formed with the first electrode.

[0063] Example 15 is the method of Example 9, where the metal-mesh portion has a predefined metal line-to-space ratio.

[0064] Example 16 is the method of any of Examples 9-15, where at least a portion of each of the first electrode, the metal-mesh portion, and the solid outer frame is embedded in a top portion of the piezoelectric layer.

[0065] Example 17 is an apparatus including a manner to perform a method as exemplified in any of Examples 9-16.

[0066] Example 18 is a machine-readable medium including code, when executed, to cause a machine to perform the method of any one of Examples 9-16.

[0067] Example 19 is a computing device. The computing device is a processor mounted on a substrate, a memory unit capable of storing data, a graphics processing unit, an antenna within the computing device, a display on the computing device, and a battery within the computing device. The computing device is a power amplifier within the processor, a voltage regulator within the processor where the processor includes solidly mounted acoustic resonator, includes a first metal region on a substrate, a piezoelectric region over the first metal region, and a second metal region over the piezoelectric region, the second metal region including an outer frame portion, a middle portion, and a metal-mesh portion between the outer frame portion and the middle portion.

[0068] Example 20 is the computing device of Example 19, where the metal- mesh portion and the outer frame portion are the same material. [0069] Example 21 is the computing device of Example 19, where the metal- mesh portion and the outer frame portion are different materials.

[0070]

[0071] Example 22 is the computing device of Example 19, where the metal- mesh portion and the outer frame portion are integrally formed with the middle portion.

[0072] Example 23 is the computing device of Example 19, where the metal- mesh portion has a predefined metal line-to-space ratio.

[0073] Example 24 is the computing device of any one of Examples 19-23, where at least a portion of each of the metal-mesh portion, the middle portion, and the outer frame portion of the second metal region is embedded in a top portion of the piezoelectric region.

[0074] Example 25 is the computing device of any one of Examples 19-24, where the processor includes a bandpass filter including the solidly mounted acoustic resonator.

[0075] Example 26 is a solidly mounted acoustic resonator. The resonator includes a first electrode, a metal-mesh frame substantially surrounding the first electrode, a solid outer frame substantially surrounding the metal-mesh frame, a second electrode, and a piezoelectric region disposed between the first electrode and the second electrode.

[0076] Example 27 is the solidly mounted acoustic resonator of Example 26, where at least a portion of each of the first electrode, the metal-mesh frame, and the solid outer frame is embedded in a surface of the piezoelectric region.

[0077] Example 28 is the solidly mounted acoustic resonator of Example 26, where the metal-mesh frame and the solid outer frame are the same material.

[0078] Example 29 is the solidly mounted acoustic resonator of Example 26, where the metal-mesh frame and the solid outer frame are different materials.

[0079] Example 30 is the solidly mounted acoustic resonator of Example 26, where the metal-mesh frame and the solid outer frame are integrally formed with the first electrode.

[0080] Example 31 is the solidly mounted acoustic resonator of Example 26, where the metal-mesh frame has a predefined metal line-to-space ratio.

[0081] Example 32 is a bandpass filter including the solidly mounted acoustic resonator of any one of Examples 26-31 . [0082] It will be obvious to those having skill in the art that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. The scope of the present invention should, therefore, be determined only by the following claims.