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KLEE, Mareike (IP DepartmentHigh Tech Campus 60, AG Eindhoven, NL-5656, NL)
MAUCZOK, Ruediger (IP DepartmentHigh Tech Campus 60, AG Eindhoven, NL-5656, NL)
JOEHREN, Michael (IP DepartmentHigh Tech Campus 60, AG Eindhoven, NL-5656, NL)
ROEST, Aarnoud (IP DepartmentHigh Tech Campus 60, AG Eindhoven, NL-5656, NL)
KLEE, Mareike (IP DepartmentHigh Tech Campus 60, AG Eindhoven, NL-5656, NL)
MAUCZOK, Ruediger (IP DepartmentHigh Tech Campus 60, AG Eindhoven, NL-5656, NL)
JOEHREN, Michael (IP DepartmentHigh Tech Campus 60, AG Eindhoven, NL-5656, NL)
| CLAIMS:
1. A device (100) comprising a semiconductor substrate layer (104) and a capacitor (102) with a bottom electrode layer (1 12), a top electrode layer (1 16) and a lead-containing dielectric layer (1 14) between the bottom and top electrode layers, wherein a bottom lead- donating layer (110) is arranged between the substrate layer and the bottom electrode layer, and a top lead-donating layer (1 18) is arranged on top of the top electrode layer.
2. A device as claimed in Claim 1, wherein the dielectric layer has a lead concentration that is substantially uniform along an axis extending from top to bottom electrode.
3. The device of claim 1 , wherein the bottom ( 110) or top (1 18) lead-donating layer comprises a ternary, quaternary or higher perovskite material.
4. The device as claimed in Claim 3, wherein at least one of the lead-donating layers comprise PbZr x Ti i. x θ 3 , 0<x<l , or La doped PbZr x Ti i -x 0 3 .
5. The device as claimed in Claim 1, wherein at least one of the lead-donating layers has a comprises a material with a lead content that is larger than the material of the dielectric layer.
6. The device as claimed in Claim 1, wherein the top lead-donating layer (1 18) is further arranged laterally adjacent to the lead-containing dielectric layer (114), such that a side face of the dielectric layer constitutes an interface with the lead-donating layer.
7. The device as claimed in Claim 6, wherein the top lead-donating layer (118) is arranged laterally around the dielectric layer (1 14) so as to constitute a protective shell.
8. The device as claimed in Claim 6, further comprising a cover layer extending on a top face of the top lead-donating layer.
9. The device as claimed in Claim 6, 7 or 8, further comprising an interconnect extending through the top lead-donating layer and the cover layer so as to extend to the bottom electrode, which electrode comprises a ductile material.
10. The device as claimed in Claim 8 or 9, wherein a resistor is provided on top of the cover layer.
1 1. The device (200) of claim 1, wherein the capacitor (202) further comprises at least one additional capacitive layer sequence of an intermediate electrode layer (230) and a lead- containing intermediate dielectric layer (232) between the first dielectric layer (214) and the top electrode layer (216).
12. The device of claim 11, further comprising means (234) for applying a bias voltage between two electrode layers selected from the group of the bottom, the at least one intermediate and the top electrode layers.
13. The device of claim 1, which further comprises an ESD protection device (D2) integrated in the semiconductor substrate layer.
14 A method of manufacturing a device that comprises a semiconductor substrate layer and a capacitor, comprising the steps: providing a semiconductor substrate layer (104); depositing a bottom electrode layer (1 12); depositing a lead-containing dielectric layer (1 14) on the bottom electrode layer; - depositing a top electrode layer (118) on the dielectric layer; wherein an bottom lead-donating dielectric layer (1 10) is deposited before depositing the bottom electrode layer on it, and a top lead-donating layer (118) is deposited on top of the top electrode layer. |
Device with Pb-based high-K. dielectric thin-film capacitor comprising Pb-donating layers
FIELD OF THE INVENTION
The present invention relates to a device comprising a semiconductor substrate layer and a capacitor with a bottom electrode layer, a top electrode layer and a lead- containing dielectric layer between the bottom and top electrode layers. The invention further relates to a method for fabricating a device that comprises a semiconductor layer and a capacitor.
BACKGROUND OF THE INVENTION
US 2003/0201497 Al describes a device with a MIM capacitor on a semiconductor substrate. The MIM capacitor has a dielectric layer between a bottom electrode layer and a top electrode layer. The dielectric layer is in different examples made of PZT (Pb(ZrJi)O 3 ) or PLZT ((Pb 5 La)(Zr 5 Ti)O 3 ). One capacitor structure is described in this document as having a silicon oxide film of 100 nm thickness on a p-type Si substrate, a Pt film of 200 nm thickness over the silicon oxide film, a Ti film of 6 nm over the Pt film, and then a ferroelectric PZT film with a thickness of 500 nm. The Pt film serves as a bottom electrode and the Ti film serves as a seed layer for growing the PZT film. The PZT film is covered with an IrO 2 film of 500 nm thickness, which serves as the top electrode.
The document mentions in paragraph [0086] as an advantage of Pb-based materials such as PZT that they are easily revaporized after deposition. The positive effect is described as a support of the formation of particularly small crystal grains of the dielectric material, which helps to keep leakage currents low in a capacitor. However, such revaporation may lead to an inhomogenous chemical composition of Pb-based dielectric materials under typical processing temperatures in the range of several hundred degrees Celsius during fabrication, which in turn negatively affects the overall relative permittivity k of a dielectric layer formed from a Pb-based dielectric material.
For various application purposes such as, for instance, protection against electrostatic discharge (ESD) or filter circuits for analog signals, it would be desirable to improve a device with a MIM capacitor structure that comprises a Pb-containing dielectric layer so as to provide the MIM capacitor with a particularly high relative permittivity of its dielectric layer.
SUMMARY OF THE INVENTION
According to a first aspect of the invention a device comprising a semiconductor substrate layer and a capacitor with a bottom electrode layer, a top electrode layer and a lead- containing dielectric layer between the bottom and top electrode layers is provided. In the capacitor, a bottom lead(Pb)-donating layer is arranged between the substrate layer and the bottom electrode layer, and a top Pb-donating layer is arranged on top of the top electrode layer, which bottom and top lead-donating layers are electrically insulating.
The attribute "bottom" is used in the context of the layer structure to denote a layer that is closer to the substrate layer than another layer, which for differentiation is described using the attribute "top". The terms "bottom" and "top" are used independently from an orientation of the device in space, even though it might.
The device of the present invention comprises a capacitor structure that can be fabricated with a particularly high relative permittivity. The capacitor structure of the device of the present invention furthermore meets requirements of a very high life time.
Providing a bottom lead-donating layer between the substrate layer and the bottom electrode layer and a top lead-donating layer on top of the top electrode layer allows avoiding the negative effects of a relatively high lead oxide loss during the fabrication of Pb- based dielectric materials. The device of the first aspect of the invention is based on the perception that typical manufacturing processes of lead-containing dielectric layers involving temperatures of several hundred degrees Celsius may lead to diffusion and reaction processes, which result in a loss of lead (Pb) in at least sections of the Pb-containing dielectric layer. A lead deficiency in a dielectric layer is likely to reduce the relative permittivity of the dielectric material. The inventors have observed a concentration gradient with respect to the Pb content in prior art devices. Particularly, Pb-rich material was found at the bottom of the dielectric layer and Pb-deficient material was found towards the top of the dielectric. The inventors have understood that the provision of lead donating layers both at the top and the bottom side prevents the generation of such concentration gradient with respect to the lead content. Therefore, the resulting capacitor has thus a lead content that is substantially uniform in the direction from bottom to top electrode. As a result, variations in the concentration may be limited to 50% or less, suitably 20% or less, more suitably 10% or less, most suitably 5% or less, up to even 2% or less.
With the capacitor structure used in the device of the present invention, however, lead-donating layers between the substrate layer and the bottom electrode layer on one side, and on top of the top electrode layer, on the other side, help to prevent the lead oxide loss to avoid a degradation of the dielectric properties of this layer. This in turn allows achieving high values of the relative permittivity of the dielectric layer. In some embodiments, the relative permittivity of the dielectric layer is in the range of 1600. The top lead-donating layer, which is typically processed at several hundred degrees Celsius, affects also in a positive way the stress in the MIM capacitor stack as well as the electrode - dielectric layer interface, which further supports a high relative permittivity of the capacitor. An additional advantage of the reduction of lead loss is that the density and structure of the device is substantially homogeneous throughout the dielectric layer. Therewith, also the resistance against operation (DC) voltages is improved
The provision of the device of the first aspect of the invention is particularly useful in device applications that require capacitor structures with a high capacitance density. For instance, the provision of integrated circuits with protection elements such as diodes and/or filters, including RC filter as well as any other combination of capacitor, resistor combinations, including also π-type filters (CRC filters) is enabled. Such devices fulfill several apparently conflicting requirements: first of all, a sufficiently high capacitance density, and thus a product with proper functionality in limited size; secondly, an adequate breakdown voltage against electrostatic discharge (ESD) impulses; and thirdly, a capacitor that may be used in circuits carrying a higher DC voltage than the commonly used voltage of 3 V, for instance 6 V.
From EP 0 823 718 A2 it is known to use certain intermediate layers between an insulating substrate such as glass or A12O3, and a bottom electrode layer. The intermediate layer serves as an anti-reaction layer on glass to prevent reactions between the substrate and the bottom electrode layer, or as a planarization layer on A12O3 to avoid negative effects of a high surface roughness of the A12O3 substrate layer. TiO 2 and more complex derivative materials including PZT are listed as suitable intermediate layers. However, in agreement with the concept of EP 0 823 718 A2, which aims at avoiding interactions between the substrate and the bottom electrode layer, there is no top lead-donating layer provided or suggested in that document. In contrast, according to the present invention a provision of both, the bottom and the top lead-donating layers has been found to efficiently solve the problem of lead oxide loss caused by high temperatures used during fabrication of the device. Furthermore, a planarization layer as suggested by EP 0 823 718 A2 would not be required in
the device of the present invention. For semiconductor substrate layers can be fabricated with a high smoothness by existing processing technologies.
In the following, embodiments of the device of the first aspect of the invention will be described. The additional features of different embodiments described herein can be combined with each other to form further embodiments, unless it is explicitly mentioned or clear to a person of ordinary skill in the art from the context of the description that certain embodiments form alternatives to each other.
A first group of embodiments concerns the lead donating layers. The bottom or top lead-donating layers preferably are electrically insulating. This keeps the design and processing expenditure of the capacitor structure low.
Suitable Pb-donating layers have a perovskite crystal structure. Lead-containing perovskites form a large group of materials with a crystal structure that is suitable for integration into the capacitor structure below the bottom electrode and above the top electrode layer. As a bottom lead-donating layer, perovskite crystal structures further have suitable barrier properties to avoid reactions of the bottom electrode layer with the substrate layer or other intermediate layers such as further insolating layers. In particularly suitable embodiments, the bottom or top lead-donating layer or both mentioned layers is made of PbZr x Ti i -x 03, 0<x<l, or La doped PbZr x Ti i -x 0 3 , with 0<x<l .
The materials of the bottom and top lead-donating layer can be different from each other. A suitable thickness of the bottom or top lead-donating layer is at least 50 nm. In another embodiment a thickness of up to 300 nm can be used. .
A structure of a capacitor that is particularly suitable for preventing the loss of lead oxide in the dielectric layer has a top lead-donating layer, which is further arranged laterally adjacent to the lead-containing dielectric layer. This helps to compensate for lead oxide losses in the dielectric layer and to prevent the formation of so called 'dead' layers, which are layers with a (much) lower dielectric constant than the high-k dielectric itself. The lead donating top layer thus improves the interface of the top electrode and the dielectric thin film, and in this way particularly high relative permittivities of the dielectric thin film can be achieved. The top lead-donating layer also positively affects the stress of the total capacitor stack and in this way further supports the high relative permittivities.
In a further embodiment, an insulation layer is arranged between the substrate layer and the bottom lead-donating layer. The insulation layer may for instance be made of SiO2. An additional TiO2 layer may be provided underneath the bottom lead-donating layer,
for instance with a thickness of at least 10 ran. But also other layers such as A12O3 or ZrO2 or MgO could be applied between the substrate layer and the bottom lead donating layer.
The Pb-containing dielectric layer is in preferred embodiments a perovskite layer as well. These materials have been established in processing technology and can be fabricated with excellent quality. Very suitable materials are PZT (PbZrxTil-xO3, 0<x<l), or PLZT, i.e., La doped PbZrxTil-xO3. To avoid leakage currents, the dielectric layer is preferably a single-phase perovskite layer.
The La content in a PLZT dielectric layer can be used to optimize the electrical properties of the capacitor such as leakage current, breakdown voltage and lifetime. It should be noted, however, that also other lead containing dielectric layers can be applied. Examples are lead magnesium niobate - lead titanate layers, doped or undoped. In principle, any other lead containing dielectric layers can be used.
The thickness of the dielectric layer depends on the required capacitance density. In some embodiments, the thickness ranges between 300 and 400 nm. The capacitor structure can be modified to further increase the capacitance density by stacking capacitive layer sequences, i.e., providing at least one additional capacitive layer sequence of an intermediate electrode layer and a lead-containing intermediate dielectric layer between the first dielectric layer and the top electrode layer. Such stacked capacitor structures allow to reach relative dielectric permittivities of up to 1600. In one embodiment, the additional capacitive layer sequence repeats the material parameters and thicknesses of previously mentioned embodiments of capacitor with respect to the dielectric layer and the electrode layer.
An advantageous stacked capacitor structure has means for applying a bias voltage between two of the bottom, intermediate and top electrode layers. The device of this embodiment preferably comprises contacts and an interconnect structure, which provide a connection or are connectable to an internal or external bias voltage source.
Regarding the electrode layers, different embodiments have one or several materials of the group formed by platinum, ruthenium oxide, iridium and iridium oxide as electrode materials. Ruthenium oxide, iridium and iridium oxide are in some embodiments only used as materials for the top electrode. However, as the bottom electrode in some embodiments, the top electrode is in one embodiment formed by a Ti/Pt electrode. The thickness of the electrode layers typically ranges between 50 and 500 nm, preferably around 100 nm. Additional layers, for instance of Ti, may be present for improvement of adhesion.
Still, other metals and metal stacks may be used alternatively such as, TiW/Pt, Ta/Pt, W, Ni, Mo, Au, Cu, Ir, IrO2/Ir, Ti/Pt/Al, Ti/Ag, Ti/Ag/Ti, Ti/Ag/Ir, Ti/Ir, Ti/Pd, Ti/Agi-xPtx (0 < x < 1), Ti/Ag i -xPdx (0 < x < 1), Agi-xPtx (0 < x < 1), Ti/Pti-χAlx (O < x < 1), Pti-xAlx (0 <x < 1), Ti/Ag/Pti-xAlx (0 < x < 1), Ti/Ag/Ru, Ru, Ru/Ruθ2, Ti/Ru, Ti/Ir, Ti/Ir/Irθ2, Ti/Ru/RuxPti-χ (0 < x < 1), Ti/Ag/Ir/Irθχ (0 < x < 2), Ti/Ag/Ru/RuOx (0 < x < 2), Ti/Ag/Ru/RuxPti-x (0 < x < 1 ), Ti/Ag/Ru/RuxPti-x/RuOy (0 < x < 1 , 0 < y < 2), Ti/Ag/Ru/RuOx/RuyPti-y (0 < x < 2, 0 < y < 1), Ti/Ag/RuxPti-χ (0 < x < 1), Ti/Ag/PtχAli- x (0
< 15 x < 1), PtxAli-x/Ag/PtyAh-y (0 < x < 1, 0 < y < 1), Ti/Ag/Pt y (RhOx)i- y (0 < x < 2, 0 < y
< 1), Ti/Ag/Rh/RhOx (0 < x < 2), Rh, Rh/Rhθ2, Ti/Ag/PtxRhi-x (0 < x < 1), Ti/Ag/Pty (RhO x ) i- y /PtzRhi- z (0 < x < 2, 0 < y < 1, 0 < z < 1), Ti/AgxPti-x/Ir (0 < x < 1), Ti/AgxPti-χ/Ir/IrOy (0 < x
< 1, 0 < y < 2), Ti/AgxPti-x/PtyAli-y (0 < x < 1, 0 < y < 1), Ti/AgxPti-x/Ru (0 < x < 1), Ti/AgxPt!-χ/Ru/RuO y (0 < x < 1, 0 < y < 2), Ti/Ag/Cr, Ti/Ag/Ti/ITO, Ti/Ag/Cr/ITO, 20 Ti/Ag/ITO, Ti/Ni/ITO, Ti/Rh, Ti/Rh/Rhθ2.
As mentioned, the device of the present invention is particularly suitable for filter applications. An advantageous embodiment thus comprises a filter circuit including the capacitor. A RC, RCR or CRC filter can be arranged with another integrated circuit on a single substrate. In one embodiment, the filter circuit forms a π-filter (Pi-filter). Such Pi- filters may contain two capacitive elements and one inductive element, resulting in a particularly low impedance to source and load sides of a circuit. Using the three mentioned elements, a better high-frequency performance is obtained than with pure LC combinations. An increase in integration density can be achieved with the device of the present invention in one embodiment, which comprises an insulating cover layer or a combination or sequence of insulating cover layers on the top lead-donating layer, and deposited thereon a resistor. The cover layer is suitably the passivation layer such as known to the skilled person, for instance silicon nitride, silicon oxynitride. Alternatively, the cover layer is a intermetal dielectric layer, as known to the skilled person, including silicon oxide and any type of low-K materials. The resistor is suitably made by deposition of a layer sequence of an electrically conductive resistor layer and an electrically conductive interconnect layer, the latter having a lower electrical resistance than the resistor layer. One suitable material for the resistor layer is for instance TiW or nitrogen-doped TiW. Other resistor materials are not excluded, however. It is in this context observed that the deposition of the resistor on top of the passivation layer allows the use of a larger class of materials than conventionally applied in semiconductor devices. One such example is the application of so-called phase change
materials as known per se to the skilled person, and also including alloys such as Al-Ge. A heat treatment allows the tuning of the resistance value of such phase change materials. This allows tuning of the filter properties, for instance so as to adapt a general purpose filter to a specific frequency. The heat treatment is suitably applied with a localized heat source, such as a laser. Evidently, the presence of the resistor on top of the passivation layer also allows trimming of the resistor in a manner known to the skilled person.
In a further embodiment, the top lead donating layer extends laterally to the dielectric layer so as to constitute an interface with a side face of the dielectric layer. This embodiment has been found to be suitable for the mechanical stability of the device. Suitably, the said interface extends to at least 50% of the area of the side face of the dielectric layer. More suitably, that percentage is even higher. In case of a dielectric with an intermediate electrode between two sublayers, the top lead-donating layer most suitably extends substantially around the upper dielectric sublayer. Therewith, it constitutes a protecting shell. This construction has the advantage of improved mechanical reliability. In fact, the capacitor is designed as an isolated block within the device. During use, when stresses occur due to thermal cycling, stresses on the capacitor and the electrode-dielectric interfaces are therewith minimized.
In a further modification thereof, at least one vertical interconnect is present adjacent to the capacitor, so as to extend through the top lead-donating layer. The vertical interconnect will contact the bottom electrode. In case an intermediate electrode is present, a further vertical interconnect is suitably present. Most suitably, the interconnect comprises a ductile material. Such ductile material is well suited for releasing stress resulting from thermal cycling. The ductile material that is used for the definition of the interconnects may additionally be used for the definition of underbump metallisation to which solder bumps or the like may be attached. Suitable ductile materials include for instance Al, AlCu, AlSi, or AlCuSi. A barrier layer may be present between such ductile material and the top lead donating layer. The above mentioned resistor may be defined in the same process step as the barrier layer.
A further application that draws advantages from the structure of the device is an ESD protection circuit integrated on the semiconductor substrate layer. An ESD protection device used in combination with the capacitor may for instance be a diode, such as a Zener diode, or a bipolar transistor. Particularly, such ESD protection device allows a system level protection of at least 8 kV. The combination of such filters with ESD protection elements is advantageous in that the diode can be integrated in the filter design, so as to meet the
requirements for signal transmission as have been set by standards such as HDMI and USB. With increasing speed of signal transmission, and thus increasing frequencies, these requirements are more stringent and require larger capacitors. However, due to the need to withstand ESD pulses and the ability to use higher operation voltages, the dielectric thickness cannot be reduced. The present invention allows to meet all those criteria.
According to a second aspect of the invention, a method for fabricating a device that comprises a semiconductor substrate layer and a capacitor is provided. The method has the steps
- providing a semiconductor substrate layer; - depositing a bottom electrode layer;
- depositing a lead-containing dielectric layer on the bottom electrode layer;
- depositing a top electrode layer on the dielectric layer.
In the method of the second aspect of the invention, an electrically insulating bottom lead-donating layer is deposited before depositing the bottom electrode layer on it, and a top lead-donating layer is deposited on top of the top electrode layer.
Preferred embodiments of the invention are also defined in the dependent claims.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. In the following drawings
Fig. 1 shows a schematic cross-sectional view of a first embodiment of an integrated-circuit device according to the invention;
Fig. 2 shows a schematic cross-sectional view of a second embodiment of an integrated-circuit device according to the invention; Fig. 3 shows an electrical diagram of an integrated circuit according to an embodiment of the invention.
DETAILED DESCRIPTION OF EMBODIMENTS
Fig. 1 shows a schematic cross-sectional view of a first embodiment of an integrated-circuit device 100 according to the invention. To reduce the graphical representation of the device to those sections, which are essential for describing the present embodiment, only a capacitor 102 is shown in Fig. 1. The capacitor 102 is fabricated on a silicon substrate 104, which is p-conductive. However, p-conductivity is not a prerequisite for an integration of the capacitor with other electronic circuit elements in an integrated
circuit on one substrate. This holds for any doping type and doping level of the Si substrate 104, as well as for any other substrate material, which is not Si.
The substrate contains in another section, which is not shown in Fig. 1 , active of passive electronic elements such as ESD protection diodes or passive electronic components such as resistors. On the substrate 104, a SiO 2 layer 106 is deposited, which is covered by a TiO 2 layer 108. On top of the TiO 2 layer 108, a bottom lead-donating layer 1 10 is provided. The bottom lead-donating layer 110 is made of PZT or PLZT. The bottom lead-donating layer 1 10 has a thickness of about 100 nm. The thickness should not be lower than 50 nm. In other embodiments, the thickness can also be higher than 100 nm, such as 300 nm. In contrast, the TiO 2 layer has a thickness of 10 nm or more.
On top of the bottom lead-donating layer 1 10, a bottom electrode made of platinum Pt is deposited with a thickness of between 50 and 500 nm. The bottom electrode 112 is lithographically patterned, before a Pb-containing high-K dielectric layer 114 such as PLZT is deposited and lithographically patterned. Suitably, the patterning of the bottom electrode layer is such that there is a direct interface between the bottom lead donating layer and the dielectric layer. This tends to be beneficial for the growth of the material according to the desired crystallographic structure, with a minimum of dislocations. In an alternative embodiment, the dielectric and the top electrode are deposited, and the stack is then patterned top down to the bottom electrode, followed by a deposition of the cover layer. On top of the dielectric layer 114, a top electrode is deposited, which in the present example is a Pt electrode, but can be made from another suitable metal or from ruthenium oxide, iridium or iridium oxide. The top electrode 1 16 is also lithographically patterned to cover only a section of the underlying dielectric layer 114.
In an alternative fabrication method, the bottom electrode is deposited, followed by a deposition of the Pb-containing dielectric layer and of the top electrode. After these deposition processes, the top electrode is lithographically patterned, followed by patterning the Pb containing dielectric layer and then the Pt bottom electrode.
Furthermore, a further PZT or PLZT layer as a top lead-donating layer 1 18 is deposited on top of the top electrode layer 1 16. The top lead-donating layer 1 18 is also adjacent to a side face 1 14.1 of the dielectric layer 1 14. The structure is covered by an electrically insulating layer, which in the present embodiment is a silicon nitride layer 120. Vertical interconnects to the bottom electrode layer 1 12 and to the top electrode layer 116 are fabricated using an intermediate nitrogen-doped titanium tungsten TiW(N) layer 122, covered with a contact-layer material such as Al, Al doped with Si or Cu or both.
The TiW(N) layer can either act only as a barrier layer between the top electrode and the metal contact. The TiW(N) layer can also be used to realize in a special region on the cover layer a resistor. This resistor can be located directly on the cover layer on top of the capacitor structure. The resistor can also be located on the cover layer next to the capacitor. The contact holes can be filled with any suitable conductive material, such as Al,
Cu, Pt or an alloy of Al and Cu or of Al and Si or combinations of Ti and Al or Ti and Cu or Ti and an alloy of Al and Cu or of Ti and Al and Si or combinations of TiW and Al or TiW and Cu or TiW and an alloy of Al and Cu or of Al and Si or combinations of TiW or TiWN - both also referred to as TiW(N) - and Al or TiW(N) and Cu or TiW(N) and an alloy of Al and Cu or Al and Si or combinations of TiN and Al or TiN and Cu or TiN an alloy of Al and Cu or of Al and Si.
The provision of the resistor layer 122 allows an increase of the integration density. It avoids the integration of separate resistor elements in different chip areas. The resistance can be controlled by the thickness of the resistor layer, the length of the resistor and by the composition of the TiW alloy, including, as an option, for example a variation of the N content of the resistor layer to optimize the resistance and temperature dependence of the resistor. Preferably, the composition of the TiWN is also chosen to provide a material with a sufficient temperature stability of the resistivity.
In an alternative, the resistor layer can be applied also on top of the contact layer material 124. In this case barrier layer 122 is applied, which can be TiN or TiW or TiWN, on which a contact material 124 such as Al or Al doped with Si or any other material is applied. On top of the contact material 124 the resistor layer which can be TiW(N) but also any other resistor layer such as SiCr or SiCr doped with O is deposited and lithographically patterned. The capacitor structure 102 has the advantage of achieving a particularly homogeneous composition of the PLZT dielectric layer 114 by preventing the occurrence of or reducing a Pb concentration gradient. The inventors found that during fabrication, in the absence of the lead-donating layers 110 and 118, typical processing step in the fabrication that involve higher temperatures in the range of several hundred degrees Celsius would result in a concentration gradient with Pb-rich material at the bottom of the dielectric layer 1 14 and Pb-deficient material towards the top of the dielectric layer 1 14, driven by an lead oxide loss from the dielectric layer. Typical temperatures occurring during the processing of the capacitor range between 600 and 800 °C.
In the fabrication process of the device of the present embodiment, such temperatures are sufficient to activate a lead donation processes. At operating conditions, for
comparison, the occurring maximum temperatures will be much lower, e.g., about 150 0 C (at most) and not be high enough to activate the lead donation. The bottom lead-donating layer is able to prevent a net lead oxide diffusion from the dielectric layer 114 through the bottom electrode or to compensates an occurring out-diffusion of lead oxide from the dielectric layer 1 14. The top lead-donating layer is able to prevent or compensate an outdiffusion of lead oxide through the top surface of the dielectric layer, which thus helps to deactivate a major process of lead oxide loss and improves the top electrode dielectric interface.
For instance, a diffusion and reaction of TiO 2 with PbO in the growing perovskite layer to PbTiO 3 has been found to result in a lead loss in the dielectric layer in standard processes according to the prior art. Such lead loss is avoided in the capacitor structure of the present embodiment.
It should be noted that the top lead-donating layer deposition also modifies the total stress of the capacitor stack and in this way improves the relative permittivity of the dielectric layer. The lead donating layer has further the advantage of preventing reactions of the top electrode layer 216 with aggressive components during the fabrication, like, e.g., hydrogen.
Lifetime investigations have shown that a lifetime fulfilling the requirements for device applications is achieved with the described structure.
Fig. 2 shows a schematic cross-sectional view of a second embodiment of an integrated-circuit device 200 according to the invention. A capacitor 202 resembles the capacitor 102 in many structural features. However, it has a stacked structure with two dielectric layers and three electrode layers. In the following description, reference labels with identical last two digits will be used for structural elements of the integrated-circuit device 200 that are functionally equivalent to corresponding structural elements of the integrated circuit-device 100 of Fig. 1. Thus, the reference labels differ only in the first digit, which was "1" for the integrated-circuit device 100 of Fig. 1, and is "2" for the integrated-circuit device 200 of Fig. 2. The following description concentrates on differences between the integrated circuit devices 100 and 200.
The layer structure of the capacitor 202 comprises an additional capacitive layer stack with an intermediate electrode 230 and a second dielectric layer 232 between the first dielectric layer 214 and the top electrode 216. The top lead-donating layer 218 laterally abuts the second dielectric layer 232 and the first dielectric layer 214. In the present embodiment, an intermediate contact 234 is provided to the intermediate electrode layer 230. The contacts 224 and 226 to the bottom and top electrode layers are electrically connected with each other.
A lithographically patterned resistor layer 222 is provided on the electrode layers 212, 224 and 234. The resistor layer can be made of TiW(N) or another suitable resistor material.
The realization of the resistor layer and the contact layer can also be achieved in alternative structure, which is not shown here. In an alternative processing sequence for this alternative structure, first the interconnect layer is deposited. Here, a combination of a barrier layer and an interconnect layer, where as barrier layer TiN or TiW(N) or any other suited barrier layer, and, as interconnect layer, Al or Al doped with Cu or Al doped with Si or Al doped with Cu and Si are deposited and patterned. On top, the resistor layer of, e.g. TiW(N) or another suitable material such as SiCr or SiCr doped with O is deposited. Both metal layers are then patterned to form locally with the TiW(N) also a resistor region, and with the Al or Al(Cu) the layer interconnects to diodes, resistors, or other capacitors on the same chip. The device is finally covered with a cover layer, which could be SiN or another suitable insulating material. In a further alternative approach, the stacking of capacitive layer structures is repeated not only two, but three or more times.
Fig. 3 shows an electrical diagram of an integrated circuit 300. The integrated circuit 300 is designed for a microphone. The circuit comprises an input structure 302 and an output structure 304. The input structure 302 has an input (MiCin), a protection element D and a band pass filter 306. A band pass filter has a frequency pass band and is therefore also called a pass-band filter. The protection element D in this example is a diode. A Zener diode is suitable embodiment, particularly in combination with a connection to a well-conducting substrate zone. This enables a rapid removal of large voltage peaks and the associated heat. Most suitable is the use of a back-to-back diode as the protection element D. The band pass (or pass band) filter is in the present case a low-pass filter in the form of a B-type filter comprising a first and a second capacitor Cl and C2, and a resistor Rl . The capacitors Cl and C2 are connected between the supply line and ground GND.
The output structure 304 is differential and comprises a first channel 308 and a second channel 310. The first channel 308 comprises a coupling capacitor C6, an output MicP and further a filter 312. This filter is a B(Pi)-type filter comprising capacitors C2, C4 and a resistor R3. The second channel 310 comprises a coupling capacitor C7, an output MicN and another filter. This filter is a B(Pi)-type filter comprising capacitors C3, C5 and a resistor R4. These capacitors have for instance a capacitance of 1 nF, while the capacitors C6, C7 have a capacitance of 6 nF. These values are however open to optimization and dependent
on a specific application. It however appears suitable that the coupling capacitors C6, C7 have a larger capacitance value than the filtering capacitors Cl -C 5. The second channel 310 further comprises a resistor R2, which acts as a delay line and/or current divider.
The circuit further comprises a voltage supply line 314. This voltage supply line is provided with an input (bias), and extends to the input structure 302 while passing the resistor R2 in the second channel 310 of the output structure 304. The channels 308, 310 of the output structure and the voltage supply line 314 are all provided with protection elements D2. These are needed to protect the circuit against ESD pulses entering from the side of the output, for instance during assembly. The protection elements D2 are furthermore desired to take away any voltage peaks that have been flowing through the integrated circuit. Even though the integrated circuit may reduce the ESD pulse from 100 V to 10 V and take away 99 % of its intensity, the 10 V peak may still be higher than acceptable in the external component. Such additional protection D2 may however not be needed everywhere.
The voltage supply line 314 supplies a voltage to the microphone. This microphone is an external component (not shown) that is coupled to the input MiCin. The voltage supply line is driven through its input bias from another external component. This external component is suitably an integrated circuit with driver functionality. The external component is further suitable to process the signals transmitted by the differential Output structure. In this embodiment the voltage supply line supplies a DC signal while the line from input to output transmits an AC signal.
In the present invention, the coupling capacitors C6, C7 are ferroelectric capacitors with a capacitance dependent on a bias voltage, said voltage dependence being substantially symmetric around a bias voltage of 0 Volt, and wherein the input voltage as amended by the input structure acts as the bias voltage. While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.
In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.
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