TECHNICAL FIELD

[0001] In some example embodiments, the subject matter herein generally relates to diagnosing signals at signal processing stages in a MIMO radio.

BACKGROUND

[0002] In digital wireless communications systems like cellular communications implementing Long Term Evolution (LTE) and fifth generation (5G) New Radio (NR), downlink (DL) communication is performed in the direction of a network radio unit to a mobile device or remote device. Uplink (UL) communication is performed in the direction of the mobile of remote device to one or more network radios.

[0003] A network radio unit, sometimes referred to as a radio board, a radio card, or remote radio unit (RRU) takes multiple signals from a base band unit (BBU) and feeds the signals along multiple chains of digital processing stages, converts the base band signals to radio signals, and transmits the signals to the mobile or remote device. Converting the base band signals to radio signals may include converting the digital signal to an analog signal.

[0004] The RRU receives signals from the mobile or remote device, amplifies the signals, may convert the analog signals to digital signals, feeds the signals along multiple chains of digital processing stages and sends the result to the BBU.

[0005] In these wireless communication system an important goal to send and receive the best quality of signal to a from the mobile or remote device. In modern wireless communication systems it is also an important goal to maintain the latency requirements of the wireless communication system.

[0006] At any stage in the along the signal processing chain errors may be introduced. Any of the stages in the chain of signal processing stages may introduced signal errors and/or signal distortions. Signal errors and/or signal distortions may be introduced at more than one of the signal processing stages.

[0007] When a degradation of the wireless signals is observed or detected, it may be difficult or impossible to determine where in the signal processing stages an error is introduced. The ability to compare signals at different stages alone the chain of signal processing stages is necessary to determine where errors in the signal are introduced.

[0008] Thus, there is a need to analyze the signals at different and/or multiple stages in the chain of signal processing stages.

SUMMARY

[0009] In one general aspect, data capture apparatus may include a Graphical User Interface (GUI) configured to: control signal data capture, process signal data captured, and analyze the signal data that has been processed. The data capture apparatus may include a Field Programmable Gate Array (FPGA) hub; and at least two FPGA Multiple Input Multiple Output (MIMO) radio boards where each of the at least two FPGA MIMO radio boards is coupled with the GUI via the FPGA hub, and where the GUI controls the signal data capture, processing of the signal data captured in each of the at least two FPGA MIMO radio boards either alone or in combination, and analysis of the signal data processed. Where the signal data is captured from one or more signals going into each of a plurality of signal processing stages in each of the at least two MIMO radio boards alone or in combination, from one or more signals going out from each of the plurality of signal processing stages alone or in any combination of one or more signals going into and out of any of the plurality of signal processing stages in at least one of the at least two FPGA MIMO radio boards. Other embodiments of this aspect include corresponding computer systems, processing circuits, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the data capture apparatus.

[0010] Implementations may include one or more of the following features. The data capture apparatus where the signal data captured defines which signals to capture from which of the plurality of signal processing stages. The data capture apparatus where processing the signal data captured includes converting at least one of two signals processed such that signal data captured from a first signal is comparable with signal data captured from a second signal. The data capture apparatus where converting at least one of the two signals includes at least one of re-sampling the signal data captured such that data captured from the first and second signals have comparable sample rates, scaling amplitudes, time-aligning signals or phase aligning signals, and converting between time-domain signals and frequency domain signals, either alone or in any combination. The data capture apparatus where analyzing the signal data processed provides different aspects of the first signal the second signal, different views at similar of different signal processing stages of the plurality of signal processing stages of the at least two FPGA MIMO radio boards either alone or in combination. The data capture apparatus where each signal processing stage of the plurality of signal processing stages includes an unique address. The data capture apparatus where controlling the signal data capture is performed via an Application Program Interface (API), where one or more of the signal processing stages has a dedicated API, where an API command supports performing the signal data capture of a pair of signals including synchronizing capture of each signal such that the signal data capture starts at a correct time and for a correct duration. The data capture apparatus where the GUI provides an user with control of one or more APIs. The data capture apparatus where signal data processing includes processing I and Q data of a Quadrature Amplitude Modulated (QAM) signal. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0011] A system of one or more computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination of them installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs, FPGAs, or processor circuitry can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0012] In another general aspect, a data capture system is provided, the data capture system may include a Graphical User Interface (GUI) configured to: control signal data capture, process signal data captured, and analyze the signal data processed. The data capture system may include a computing device configured to host the GUI, a Field Programmable Gate Array (FPGA) hub, and at least two FPGA Multiple Input Multiple Output (MIMO) radio boards where each of the at least two FPGA MIMO radio boards is coupled with the GUI via the FPGA hub, and where the GUI controls the signal data capture, the processing of the signal data captured in each of the at least two FPGA MIMO radio boards either alone or in combination and analysis of the signal data processed. Where the signal data is captured from one or more signals going into each of a plurality of signal processing stages in each of the at least two MIMO radio boards alone or in combination, from one or more signals going out from each of the plurality of signal processing stages alone or in any combination, and from of one or more signals going into and out of any of the plurality of signal processing stages in at least one of the at least two FPGA MIMO radio boards. Other embodiments of this aspect include corresponding computer systems, FPGA, processor circuitry, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the data capture system.

[0013] Implementations may include one or more of the following features. The data capture system where the signal data captured defines which signals to capture from which of the plurality of signal processing stages. The data capture system where processing the signal data captured includes converting at least one of two signals processed such that signal data captured from a first signal is comparable with signal data captured from a second signal. The data capture system where converting at least one of the two signals includes at least one of re-sampling the signal data captured such that data captured from the first and second signals have comparable sample rates, scaling amplitudes, time-aligning signals or phase aligning signals, and converting between time-domain signals and frequency domain signals, either alone or in any combination. The data capture system where analyzing the signal data processed provides different aspects of the first signal the second signal, different views at similar of different signal processing stages of the plurality of signal processing stages of the at least two FPGA MIMO radio boards either alone or in combination. The data capture system where each signal processing stage of the plurality of signal processing stages includes an unique address. The data capture system where controlling the signal data capture is performed via an Application Program Interface (API), where one or more of the signal processing stages has a dedicated API, where an API command supports performing the signal data capture of a pair of signals including synchronizing capture of each signal such that the signal data capture starts at a correct time and for a correct duration. The data capture system where the computing device configured to host the GUI provides an user with control of one or more APIs via the GUI. Data where signal data processing includes processing I and Q data of a Quadrature Amplitude Modulated (QAM) signal. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0014] In yet another general aspect, a method of signal data capture and analysis is provided. The method may include triggering signal data capture from a Graphical User Interface (GUI). The method may also include processing at the GUI the signal data captured, performing analysis at the GUI of the processed signal data, where the signal data capture is triggered at one or more of a plurality of signal processing stages in a FPGA MIMO radio board either alone or in any combination, where data capture is triggered at the one or more of the plurality of signal processing stages either alone or in any combination in two or more FPGA MIMO radio boards. Other embodiments of this method include corresponding computer systems, FPGAs, processor circuitry, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the following drawings:

[0016] Fig. 1 is a diagram of an exemplary data capture system according to an embodiment;

[0017] Fig. 2 is a flowchart representing a process of MIMO gain calibration according to an embodiment;

[0018] Fig. 3 shows a raw time-domain signal of a Common Public Radio Interface (CPRI) signal according to an embodiment.

[0019] Fig. 4 shows a constellation plot for CPRI capture according to an embodiment;

[0020] Fig. 5 shows an analyzed constellation plot for CPRI according to an embodiment;

[0021] Fig. 6 shows a time domain plot according to an embodiment; and

[0022] Fig. 7 shows a Power Spectral Density (PSD) plot according to an embodiment.

DETAILED DESCRIPTION

[0023] Fig. 1 illustrates a data capture system according to one or more embodiments. The data capture system includes a FPGA Multiple Input Multiple Output (MIMO) hub, two FPGA MIMO radios 104A and 104B, and a computer hosting a Graphical User Interface (GUI) 150.

[0024] A user may control signal data capture, signal data processing, and analysis of the signals processed via the GUI hosted at computer 150. The GUI is coupled with the FPGA hub via processor control IF circuitry 118. [0025] The FPGA hub 102 includes data IF circuitry 106, data processing circuitry 108, DL processing circuitry 110, data IF circuitry 112, UL processing circuitry 114, data IF 116, data capture logic circuitry 120, and timing synchronization circuitry 122.

[0026] DL processing circuitry 110 receives signal data from data processing circuitry 108, and UL processing circuitry 114 feeds signal data into data processing circuitry 108. DL processing circuitry 110 feeds signals into data IF circuitry 112, and UL processing circuitry 114 receives signals from data IF circuitry 116.

[0027] Data capture logic circuitry 120 couples with signals feeding out of data processing circuitry 108, DL processing circuitry 110, Data IF circuitry 116, and UL processing circuitry 114.

[0028] The FPGA Ml MO radios 104A and 104B are shown in Fig. 1. Each FPGA MIMO radio 104A and 104B includes a plurality of signal processing stages, and the plurality of signal processing stages in FPGA MIMO radio 104A are identical to the plurality of signal processing stages in FPGA MIMO radio 104B where FPGA MIMO radio 104A illustrates a FPGA MIMO radio at the network side, and FPGA MIMO radio 104B illustrates a FPGA MIMO radio at a mobile or remote device side.

[0029] That is, FPGA MIMO radios 104A illustrates a signal processing chain from a radio on the network side, and FPGA MIMO radios 104B illustrates a signal processing chain from a radio on the mobile or remote device side. It is noted that one skilled in the art realizes that each FPGA MIMO radio 104A and 104B may transmit, receive, and process UL and DL signals. Each FPGA MIMO radio 104A and 104B includes a plurality of signal processing stages in the signal processing chain.

[0030] The plurality of signal processing stages in the signal processing chain for FPGA MIMO radio 104A are described. One skilled in the art will appreciate that the following description of the signal processing chain circuitry elements corresponding to each of the plurality of signal processing states in FPGA MIMO radio 104A may also apply to the corresponding signal processing chain circuitry elements corresponding to each of the plurality of signal processing states in in FPGA MIMO radio 104B where the corresponding signal processing chain circuitry elements in FPGA MIMO radio 104B are identified with the same reference numeral having a B designator.

[0031] The transmit signal processing chain of FPGA MIMO radio 104A includes a plurality of signal processing stages. The plurality of signal processing stages include: data IF circuitry 134A, Digital Up Conversion (DUC) processing circuitry 124A, carrier combiner circuitry 126A, Crest Factor Reduction (CFR) processing circuitry 128A, Digital Pre-Distortion (DPD) processing circuitry 130A, and Digital-to-Analog Convertor (DAC) circuitry 132 A.

[0032] The receive signal processing chain of FPGA MIMO radio 104A includes Analog-to-Digital Convertor (ADC) circuitry 144A, carrier splitter circuitry 142A, Digital Down Conversion (DDC) processing circuitry 140A, Automatic Gain Control (AGC) function circuitry 138A, and data IF circuitry 134A.

[0033] FPGA MIMO radio board 104A also includes timing synchronization circuitry 136A, processor control IF circuitry 146A and data capture logic circuitry 148A. Data capture logic circuitry 148A is coupled with each of the plurality of signal processing stages.

[0034] As stated above, one skilled in the art will appreciate that the above description of the signal processing chain circuitry elements corresponding to each of the plurality of signal processing states in FPGA MIMO radio 104A may also apply to the corresponding signal processing chain circuitry elements corresponding to each of the plurality of signal processing states in in FPGA MIMO radio 104B. FPGA MIMO radio 104B includes a plurality of signal processing states including: data IF circuitry 134B, Digital Up Conversion (DUO) processing circuitry 124B, carrier combiner circuitry 126B, Crest Factor Reduction (CFR) processing circuitry 128B, Digital Pre-Distortion (DPD) processing circuitry 130B, and Digital-to-Analog Convertor (DAC) circuitry 132B on the transmit signal processing chain.

[0035] FPGA MIMO radio 104B includes a plurality of signal processing states including: Analog-to-Digital Convertor (ADC) circuitry 144B, carrier splitter circuitry 142B, Digital Down Conversion (DDC) processing circuitry 140B, Automatic Gain Control (AGC) function circuitry 138B, and data IF circuitry 134B.

[0036] Each of the above identified signal processing stages may have a dedicated API. The GUI hosted at computer 150 provides a user with access to each dedicated API allowing the user to capture signal data at one or more FPGA MIMO radios, for example, FPGA MIMO radio boards 104A and 104B. The captured signal data may then be processed and analyzed via the GUI hosted at computer 150.

[0037] Fig. 2 is flowchart of an example process 200. In some implementations, one or more process blocks of Fig. 2 may be performed by a device.

[0038] As shown in Fig. 2, process 200 may include triggering signal data capture from a Graphical User Interface (GUI) at 202. For example, the data capture apparatus may trigger signal data capture according to a user input at the GUI, as described above. [0039] Signal data may be captured before and after one or more of the signal processing stages of the plurality of signal processing stages. Signal data may be captured at one or more different stages in different signal processing chains to show the effect of interference between the signal processing stages and processing chains. One skilled in the art understands that interference between the signal processing stages is usually unwanted.

[0040] As also shown in Fig. 2, process 200 may include processing at the GUI the signal data captured at 204. For example, data capture apparatus may process at the GUI the signal data captured, as described above.

[0041] A goal of the signal processing is to make two captured signal data sets comparable.

[0042] Signal processing may include: a. Converting between time-domain and frequency-domain. Converting between time-domain and frequency-domain may be performed by performing Fast Four Transform (FFT) and Inverse Fast Four Transform (I FFT) as appropriate. b. Re-sampling signal data captured. Re-sampling may be performed when two signal data captures are captured at different sampling rates. c. Complex conjugation. Complex conjugation may be performed when one or more signal processing stages of the plurality of signal processing stages has (by accident or design) performed a complex conjugate on the signal as it passes through the one or more signal processing stages. d. Time-alignment. Time-alignment is performed to enable triggering of the signal data capture of signals to start at the same point. Timealignment may include: i. integral time-alignment, which may be performed by shifting whole no. of samples is easy to get a coarse alignment. ii.fractional time-alignment, which is equivalent to shifting fractions of a sample. This may be performed via a fractional- delay filter applied to one of the signals. e. analyzing the signals to find regions of correlated samples. f. Scaling, which may be performed by multiplying one signal by a constant e.g. to make the captured signals the same power. g. Phase-alignment, which may be performed to find the best phase to make the two captured signals as close as possible to each other and apply this phase to one of the signals. h. Demodulation, where demodulation may consist of plotting the captured data on a grid and then adjusting how captured data signals are displayed to uncover patterns in the data

[0043] As further shown in Fig. 2, process 200 may include performing analysis at the GUI of the processed signal data at 206, where the signal data capture is triggered at one or more of a plurality of signal processing stages a FPGA Ml MO radio board either alone or in any combination, where data capture is triggered at the one or more of the plurality of signal processing stages either alone or in any combination in two or more FPGA MIMO radio boards at 202. For example, the data capture apparatus may perform analysis at the GUI of the processed signal data at 206, where the signal data capture is triggered at one or more of a plurality of signal processing stages in a FPGA MIMO radio board either alone or in any combination, where data capture is triggered at the one or more of the plurality of signal processing stages either alone or in any combination in two or more FPGA MIMO radio boards, as described above.

[0044] Once the signal data captured is processed, two data captured signals are comparable. These two signals may be analyzed. The analysis includes graphing the signals to show how the two data captured signals compare.

[0045] The graphing and analysis of the two data captured signals may include: a. Displaying signal modulus b. Displaying either the real or the imaginary parts of either signal. c. Displaying, the frequency-domain data which is derived from the original time domain d. Displaying display the modulus of the frequency components e. Displaying the constellation of the real and imaginary parts of the complex signals f. Calculating and displaying power spectral density (PSD) for the two signals g. Calculating and displaying the complementary cumulative density function (CCDF) of the signal powers h. Calculating the amplitude/amplitude graph for the two signals [0046] Process 200 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein. In a first implementation, the signal data captured at defines which signals to capture from which of the plurality of signal processing stages at 208.

[0047] In a second implementation, alone or in combination with the first implementation, processing the signal data captured includes converting at least one of two signals processed such that signal data captured from a first signal is comparable with signal data captured from a second signal at 210.

[0048] In a third implementation, alone or in combination with the first and second implementation, converting at least one of the two signals includes at least one of resampling the signal data captured such that data captured from the first and second signals have comparable sample rates, scaling amplitudes, time-aligning signals or phase aligning signals, and converting between time-domain signals and frequency domain signals, either alone or in any combination at 212.

[0049] In a fourth implementation, alone or in combination with one or more of the first through third implementations, analyzing the signal data processed provides different aspects of the first signal the second signal, different views at similar of different signal processing stages of the plurality of signal processing stages of the at least two FPGA MIMO radio boards either alone or in combination at 214.

[0050] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, each signal processing stage of the plurality of signal processing stages includes an unique address where signal data capture, processing and/or analysis may be performed via an API dedicated to the respective signal processing stage at 216. Thus, an API command supports performing the signal data capture of a pair of signals including synchronizing capture of each signal such that the signal data capture starts at a correct time and for a correct duration

[0051] In a sixth implementation, alone or in combination with one or more of the first through sixth implementations, the GUI provides an user with control of one or more APIs. In other words, a user may control one or more of the dedicated APIs via the GUI

[0052] In an seventh implementation, alone or in combination with one or more of the first through seventh implementations, signal data processing includes processing I and Q data of a Quadrature Amplitude Modulated (QAM) signal. [0053] Although Fig. 2 shows example blocks of process 200, in some implementations, process 200 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in Fig. 2. Additionally, or alternatively, two or more of the blocks of process 200 may be performed in parallel.

[0054] Fig. 3 shows a plot of a CPRI signal data capture. The time-domain of the raw CPRI signal is displayed at 302.

[0055] Fig. 4 shows a constellation plot of a CPRI signal data capture at a sample rate of 15360 kHz. The CPRI plot 402 shows a CPRI constellation when the time-domain signals are not aligned

[0056] Fig. 5 shows a constellation plot for a CPRI signal data capture at a sample rate of 15360 kHz. The CPRI plot 502 shows a clear constellation when the correct sample point offset for the constellation is found.

[0057] FIG. 6 shows a time domain plot comparing a DPD and PA signal. Time domain errors introduced by the PA are shown at 602.

[0058] Fig. 7 shows a power density plot comparing CFR spectrum and PA spectrum at 702.

[0059] While Figs. 3-7 show several examples of graphical representations of signal data captured, processed, and/or analyzed. One skilled in the art should understand that the concepts and techniques in the present disclosure may be applied to any stage in the signal processing chain.

[0060] According to the disclosed techniques a user may implement any desired combination of signal data analysis, processing, and analysis. Any generic GUI may be used to provide a user with the ability to perform signal data capture, processing, and analysis at any stage in the signal processing chain without specific knowledge of the various stages in the signal processing chain.

[0061] Since the implementation of the present disclosure does not require detailed knowledge of components of the signal processing stages, the implementation is not vendor dependent. Thus, the disclosed techniques may be applied to radios and components from a variety of equipment vendors.

[0062] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed features, from a study of the drawings, the disclosure, and the appended claims.

[0063] In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. [0064] A single processor, device or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. [0065] Operations like acquiring, accessing, analyzing, capturing, comparing, determining, displaying, inputting, obtaining, outputting, providing, store or storing, calculating, simulating, receiving, warning, and stopping can be implemented as program code means of a computer program and/or as dedicated hardware.

[0066] A computer program may be stored and/or distributed on a suitable medium, such as an optical storage medium or a solid-state medium, supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.