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Title:
DIFFERENTIAL CASCODE AMPLIFIER FOR OPTICAL COMMUNICATION WITH TUNABLE PASS-BAND FREQUENCY
Document Type and Number:
WIPO Patent Application WO/2019/114978
Kind Code:
A1
Abstract:
The invention provides a differential cascode amplifier for optical communication comprising a first variable resistor connected to a second variable resistor, wherein the first variable resistor is further connected to a control port of a first common control port transistor and the second variable resistor is further connected to a control port of a second common control port transistor of the cascode amplifier.

Inventors:
PIAZZON, Luca (Riesstr. 25, Munich, 80992, DE)
Application Number:
EP2017/082966
Publication Date:
June 20, 2019
Filing Date:
December 15, 2017
Export Citation:
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Assignee:
HUAWEI TECHNOLOGIES CO., LTD. (Huawei Administration Building Bantian, Longgang DistrictShenzhen, Guangdong 9, 518129, CN)
PIAZZON, Luca (Riesstr. 25, Munich, 80992, DE)
International Classes:
H03F3/45; H03F3/08; H03F3/193
Foreign References:
US7786807B12010-08-31
US20160036393A12016-02-04
Other References:
None
Attorney, Agent or Firm:
KREUZ, Georg (Huawei Technologies Duesseldorf GmbH, Riesstr. 8, Munich, 80992, DE)
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Claims:
CLAIMS

1. A differential cascode amplifier (100) for optical communication comprising a first variable resistor (101) connected to a second variable resistor (102), wherein the first variable resistor (101) is further connected to a control port (l03c) of a first common control port transistor (103) and the second variable resistor (102) is further connected to a control port (l04c) of a second common control port transistor (104) of the cascode amplifier (100).

2. The differential cascode amplifier (200) according to claim 1, wherein the differential cascode amplifier (200) further comprises a first voltage source (201), wherein the first voltage source (201) is connected to the first variable resistor (101), and wherein the first voltage source (201) is connected to the second variable resistor (102).

3. The differential cascode amplifier (200) according to claim 1 to 2, wherein the differential cascode amplifier (200) further comprises a first output port (202) and a second output port (203), wherein the first output port (202) is connected to the first common control port transistor (101), and wherein the second output port (203) is connected to the second common control port transistor (102).

4. The differential cascode amplifier (200) according to claim 3, wherein the connection of the first common control port transistor (101) to the first output port (202) comprises that the first output port (202) is connected to an output port (103o) of the first common control port transistor (103), and wherein the connection of the second common control port transistor (104) to the second output port (203) comprises that the second output port (203) is connected to an output port (104o) of the second common control port transistor (104).

5. The differential cascode amplifier (200) according to any one of the preceding claims, wherein the differential cascode amplifier (200) further comprises a first resistor (204), a second resistor (205) and a second voltage source (206), wherein the first resistor (204) is connected to the first common control port transistor (103), the second resistor (205) is connected to the second common control port transistor (104), and the first resistor (204) and the second resistor (205) are connected to the second voltage source (206).

6. The differential cascode amplifier (200) according to claim 5, wherein the connection of the first resistor (204) to the first common control port transistor (103) comprises that the first resistor (204) is connected to an output port (103o) of the first common control port transistor (103), and wherein the connection of the second resistor (205) to the second common control port transistor (104) comprises that the second resistor (205) is connected to an output port (104o) of the second common control port transistor (104).

7. The differential cascode amplifier (200) according to any one of claims 1 to 6, wherein the differential cascode amplifier (200) further comprises a first common input port transistor (207), a second common input port transistor (208) and a first current source (209), wherein the first common input port transistor (207) is connected to the first common control port transistor

(103), and the second common input port transistor (208) is connected to the second common control port transistor (104), and the first current source (209) is connected to the first common input port transistor (207) and to the second common input port transistor (208).

8. The differential cascode amplifier (200) according to claim 7, wherein the connection of the first common input port transistor (207) to the first common control port transistor (103) comprises that an output port (207o) of the first common input port transistor (207) is connected to an input port (l03i) of the first common control port transistor (103), wherein the connection of the second common input port transistor (208) to the second common control port transistor

(104) comprises that an output port (208o) of the second common input port transistor (208) is connected to an input port (l04i) of the second common control port transistor (104), and wherein the connection of the first current source (209) to the first common input port transistor (207) and to the second common input port transistor (208) comprises that the first current source (209) is connected to an input port (207i) of the first common input port transistor (207) and to an input port (208i) of the second common input port transistor (208).

9. The differential cascode amplifier (200) according to claim 7 or 8, wherein the differential cascode amplifier (200) further comprises a first input port (210) and a second input port (211), wherein the first input port (210) is connected to the first common input port transistor (207), preferably to a control port (207c) of the first common input port transistor (207), and wherein the second input port (211) is connected to the second common input port transistor (208), preferably to a control port (208c) of the second common input port transistor (208).

10. The differential cascode amplifier according to any one of the claims 1 to 9, wherein the first variable resistor (101) is implemented by means of a transistor (401), or a potentiometer (501), or a switchable resistor (601), and the second variable resistor (102) is implemented by means of a transistor (402), or a potentiometer (502), or a switchable resistor (602).

11. The differential cascode amplifier (400) according to any one of the claims 1 to 10, wherein the first variable resistor (101) is implemented by means of a transistor (401), and wherein the differential cascode amplifier (400) further comprises a control voltage source (403) connected to the first variable resistor (101), preferably connected to a control port (40 lc) of the first variable resistor (101), and wherein the differential cascode amplifier (400) is configured to control the first variable resistor (101) according to a control voltage provided by the control voltage source (403).

12. The differential cascode amplifier (400) according to claim 11, wherein the second variable resistor (102) is implemented by means of a transistor (402), wherein the control voltage source

(403) is further connected to the second variable resistor (102), preferably connected to a control port (402c) of the second variable resistor (102), and wherein the differential cascode amplifier (400) is further configured to control the second variable resistor (102) according to a control voltage provided by the control voltage source (403).

13. A method (700) for operating a differential cascode amplifier (100) for optical communication that comprises a first variable resistor (101) connected to a second variable resistor (102), wherein the first variable resistor (101) is further connected to a control port (l03c) of a first common control port transistor (103) of the cascode amplifier (100) and the second variable resistor (102) is further connected to a control port (l04c) of a second common control port transistor (104) of the cascode amplifier (100), the method (700) comprising the step of tuning (701), by the first variable resistor (101) and the second variable resistor (102), a pass-band frequency response of the differential cascode amplifier (100).

Description:
DIFFERENTIAL CASCODE AMPLIFIER FOR OPTICAL COMMUNICATION WITH TUNABLE PASS-BAND FREQUENCY

TECHNICAL FIELD

The present invention relates to the field of optical communication technology and in particular to a differential cascode amplifier for optical communication and an operating method thereof. The differential cascode amplifier specifically allows for tuning a pass-band frequency.

BACKGROUND

Conventional amplifiers for optical communication lead to high inter symbol interference (ISI) when the conventional amplifier’s bandwidth is narrower then approximately 70% the bit-rate of a communication standard.

In contrary, poor optical signal to noise ratio (OSNR) is obtained if the conventional amplifier’s bandwidth is excessively wider then approximately 70% the bit-rate of the communication standard. As a consequence, the conventional amplifier’s bandwidth used in optical communication has to be optimized according to the target bit-rate of the communication standard.

However, accurate prediction of the bandwidth in optical transmitters and receivers (in which the conventional amplifier is applied) is not an easy task, because it depends on an interconnection of several blocks that cannot be simulated in a proper manner. Moreover, the frequency response depends on technological and manufactural variations. Finally, a same optical module can be applied in different communication standards with different targets for the bit-rate, thus requiring different bandwidth in which ISI/SNR trade-off is optimal.

In such a scenario, amplifiers with tunable pass-band frequency are of high interest in order to optimize the ISI/SNR trade-off directly in field with best results. An approach to realize conventional differential amplifiers with tunable pass-band frequency response is based on introducing varactors, variable inductors and variable resistors at an output side of the conventional differential amplifier.

SUMMARY

In view of the above-mentioned problems and disadvantages, the present invention aims to improve the conventional differential amplifier.

Embodiments of the invention in particular allows for an optimization of the ISI/OSNR trade- off in transmitter and receiver chains for optical communication that use the differential cascode amplifier according to the present invention.

By using a differential cascode amplifier with tunable pass-band frequency response according to the present invention, the bandwidth of optical transmitters and receivers can be optimized directly in field (i.e. during operation) with best results. In optical systems that are based on differential digital sources in order to improve speed and quality of a signal, a preferred solution to achieve tuning of the bandwidth is based on differential cascode amplifiers with tunable pass- band frequency response according to the present invention.

More specifically the differential cascode amplifier according to embodiments of the present invention has the following advantages in view of the prior art:

1. Higher integration level: The proposed scheme does not require inductors and variable inductors, allowing an easy integration in monolithic microwave integrated circuit, MMIC, technologies.

2. Higher operation frequency: The differential cascode amplifier according to the present invention does not require inductors and variable inductors, which are unfeasible with low losses at high frequency, thus minimizing high frequency losses.

3. Higher linearity: The variable components used in the differential cascode amplifier according to the present invention, e.g. the variable resistors, are inserted in a gate branch of a common-gate transistors where the radio frequency signal has a very small amplitude. As a consequence, the variable components operate with small signal levels, thus with a negligible contribution to non-linearity.

4. Higher reliability: The variable components used in the differential cascode amplifier according to the present invention, e.g. the variable resistors, are inserted in a gate branch of common-gate transistors where DC voltage and current have the smallest amplitude. As a consequence, they are not stressed in terms of power handling.

The object of the present invention is achieved by the solution provided in the enclosed independent claims. Advantageous implementations of the present invention are further defined in the dependent claims.

A first aspect of the present invention provides a differential cascode amplifier for optical communication comprising a first variable resistor connected to a second variable resistor, wherein the first variable resistor is further connected to a control port of a first common control port transistor and the second variable resistor is further connected to a control port of a second common control port transistor of the cascode amplifier.

In a first implementation form of the differential cascode amplifier according to the first aspect, the differential cascode amplifier further can comprise a first voltage source, wherein the first voltage source can be connected to the first variable resistor, and wherein the first voltage source can be connected to the second variable resistor.

In a second implementation form of the differential cascode amplifier according to the first aspect, the differential cascode amplifier further can comprise a first output port and a second output port, wherein the first output port can be connected to the first common control port transistor, and wherein the second output port can be connected to the second common control port transistor.

In a third implementation form of the differential cascode amplifier according to the first aspect, the connection of the first common control port transistor to the first output port can include that the first output port can be connected to an output port of the first common control port transistor, and the connection of the second common control port transistor to the second output port can include that the second output port can be connected to an output port of the second common control port transistor.

In a fourth implementation form of the differential cascode amplifier according to the first aspect, the differential cascode amplifier further can include a first resistor, a second resistor and a second voltage source, wherein the first resistor can be connected to the first common control port transistor, the second resistor can be connected to the second common control port transistor, and the first resistor and the second resistor can be connected to the second voltage source.

In a fifth implementation form of the differential cascode amplifier according to the first aspect, the connection of the first resistor to the first common control port transistor can include that the first resistor can be connected to an output port of the first common control port transistor, and the connection of the second resistor 205 to the second common control port transistor can include that the second resistor can be connected to an output port of the second common control port transistor.

In a sixth implementation form of the differential cascode amplifier according to the first aspect, the differential cascode amplifier further can include a first common input port transistor, a second common input port transistor and a first current source, wherein the first common input port transistor can be connected to the first common control port transistor, and the second common input port transistor can be connected to the second common control port transistor, and the first current source can be connected to the first common input port transistor and to the second common input port transistor.

In a seventh implementation form of the differential cascode amplifier according to the first aspect, the connection of the first common input port transistor to the first common control port transistor can include that an output port of the first common input port transistor can be connected to an input port of the first common control port transistor, wherein the connection of the second common input port transistor to the second common control port transistor can include that an output port of the second common input port transistor can be connected to an input port of the second common control port transistor, and wherein the connection of the first current source to the first common input port transistor and to the second common input port transistor can include that the first current source can be connected to an input port of the first common input port transistor and to an input port of the second common input port transistor.

In an eighth implementation form of the differential cascode amplifier according to the first aspect, the differential cascode amplifier further can include a first input port and a second input port, wherein the first input port can be connected to the first common input port transistor, preferably to a control port of the first common input port transistor, and wherein the second input port can be connected to the second common input port transistor, preferably to a control port of the second common input port transistor.

In a ninth implementation form of the differential cascode amplifier according to the first aspect, the first variable resistor can be implemented by means of a transistor, or a potentiometer, or a switchable resistor, and the second variable resistor can be implemented by means of a transistor, or a potentiometer, or a switchable resistor.

In a tenth implementation form of the differential cascode amplifier according to the first aspect, the first variable resistor can be implemented by means of a transistor, and the differential cascode amplifier further can comprise a control voltage source connected to the first variable resistor, preferably connected to a control port of the first variable resistor, and the differential cascode amplifier can be configured to control the first variable resistor according to a control voltage provided by the control voltage source.

In an eleventh implementation form of the differential cascode amplifier according to the first aspect, the second variable resistor can be implemented by means of a transistor, wherein the control voltage source further can be connected to the second variable resistor, preferably can be connected to a control port of the second variable resistor, and wherein the differential cascode amplifier further can be configured to control the second variable resistor according to a control voltage provided by the control voltage source.

A second aspect of the present invention provides a method for operating a differential cascode amplifier for optical communication that comprises a first variable resistor connected to a second variable resistor, wherein the first variable resistor is further connected to a control port of a first common control port transistor of the cascode amplifier and the second variable resistor is further connected to a control port of a second common control port transistor of the cascode amplifier, the method comprising the step of tuning, by the first variable resistor and the second variable resistor, a pass-band frequency response of the differential amplifier.

In a first implementation form of the method according to the second aspect, the differential cascode amplifier further can comprise a first voltage source, wherein the first voltage source can be connected to the first variable resistor, and wherein the first voltage source can be connected to the second variable resistor.

In a second implementation form of the method according to the second aspect, the differential cascode amplifier further can comprise a first output port and a second output port, wherein the first output port can be connected to the first common control port transistor, and wherein the second output port can be connected to the second common control port transistor.

In a third implementation form of the method according to the second aspect, the connection of the first common control port transistor to the first output port can include that the first output port can be connected to an output port of the first common control port transistor, and the connection of the second common control port transistor to the second output port can include that the second output port can be connected to an output port of the second common control port transistor.

In a fourth implementation form of the method according to the second aspect, the differential cascode amplifier further can include a first resistor, a second resistor and a second voltage source, wherein the first resistor can be connected to the first common control port transistor, the second resistor can be connected to the second common control port transistor, and the first resistor and the second resistor can be connected to the second voltage source.

In a fifth implementation form of the method according to the second aspect, the connection of the first resistor to the first common control port transistor can include that the first resistor can be connected to an output port of the first common control port transistor, and the connection of the second resistor 205 to the second common control port transistor can include that the second resistor can be connected to an output port of the second common control port transistor.

In a sixth implementation form of the method according to the second aspect, the differential cascode amplifier further can include a first common input port transistor, a second common input port transistor and a first current source, wherein the first common input port transistor can be connected to the first common control port transistor, and the second common input port transistor can be connected to the second common control port transistor, and the first current source can be connected to the first common input port transistor and to the second common input port transistor.

In a seventh implementation form of the method according to the second aspect, the connection of the first common input port transistor to the first common control port transistor can include that an output port of the first common input port transistor can be connected to an input port of the first common control port transistor, wherein the connection of the second common input port transistor to the second common control port transistor can include that an output port of the second common input port transistor can be connected to an input port of the second common control port transistor, and wherein the connection of the first current source to the first common input port transistor and to the second common input port transistor can include that the first current source can be connected to an input port of the first common input port transistor and to an input port of the second common input port transistor.

In an eighth implementation form of the method according to the second aspect, the differential cascode amplifier further can include a first input port and a second input port, wherein the first input port can be connected to the first common input port transistor, preferably to a control port of the first common input port transistor, and wherein the second input port can be connected to the second common input port transistor, preferably to a control port of the second common input port transistor.

In a ninth implementation form of the method according to the second aspect, the first variable resistor can be implemented by means of a transistor, or a potentiometer, or a switchable resistor, and the second variable resistor can be implemented by means of a transistor, or a potentiometer, or a switchable resistor.

In a tenth implementation form of the method according to the second aspect, the first variable resistor can be implemented by means of a transistor, and the differential cascode amplifier further can comprise a control voltage source connected to the first variable resistor, preferably connected to a control port of the first variable resistor, and the differential cascode amplifier can be configured to control the first variable resistor according to a control voltage provided by the control voltage source.

In an eleventh implementation form of the method according to the second aspect, the second variable resistor can be implemented by means of a transistor, wherein the control voltage source further can be connected to the second variable resistor, preferably can be connected to a control port of the second variable resistor, and wherein the differential cascode amplifier further can be configured to control the second variable resistor according to a control voltage provided by the control voltage source.

It has to be noted that all devices, elements, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms of the present invention will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

Fig. 1 shows a differential cascode amplifier according to an embodiment of the present invention,

Fig. 2 shows a differential cascode amplifier according to an embodiment of the present invention in more detail, Fig. 3 shows schematic models of a transistor,

Fig. 4 shows another differential cascode amplifier according to an embodiment of the present invention,

Fig. 5 shows another differential cascode amplifier according to an embodiment of the present invention,

Fig. 6 shows another differential cascode amplifier according to an embodiment of the present invention, and

Fig. 7 shows a schematic overview of a method according to an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Fig. 1 shows a particular of a differential cascode amplifier 100 according to an embodiment of the present invention. The differential cascode amplifier 100 is in particular suitable for optical communication, e.g. for handling frequencies that are used for optical communication, and is implemented by means of a common cascode configuration. The differential cascode amplifier 100 is in particular illustrated by the rectangle that is shown in Fig. 1 and that contains further circuitry. The rectangle in particular illustrates that the differential cascode amplifier 100 may be in principle a conventional cascode amplifier that includes further non-conventional circuitry, wherein the advantageous effect of the present invention is based on the further circuitry.

The differential cascode amplifier 100 comprises a first variable resistor 101 and a second variable resistor 102. As it is illustrated in Fig. 1 the first variable resistor 101 and the second variable resistor 102 are connected with each other.

The first variable resistor 101 and/or the second variable resistor 102 can be implemented in several ways. Each of them can e.g. be a transistor, a potentiometer, a rheostat or a switchable resistor. In particular, a variable resistor can be any component with at least two terminals whose constitutive behavior can be described with the equation I = k · V, where I is a current flowing across the terminals and V is a voltage drop across the terminals, wherein a possibility of changing or adjusting the parameter k in some way is given, e.g. by mechanical variation, voltage or current being applied to a third terminal of the variable resistor, or others.

The first variable resistor 101 is further connected to a control port l03c of a first common control port transistor 103 and the second variable resistor 102 is further connected to a control port l04c of a second common control port transistor 104 of the cascode amplifier 100. In other words, the first variable resistor 101 and the second variable resistor 102 are inserted in a control port branch of the first common control port transistor 103 and the second common control port transistor 104 of the differential cascode amplifier 100. This can be considered the core of the invention, since it allows for tuning of the pass-band frequency response of the differential cascode amplifier 100, and allows for achieving the previously highlighted advantages in view of the prior art.

The first common control port transistor 103 or the second common control port transistor 104 can be implemented by using any kind of transistor known in the prior art. Also all further transistors which are going to be described in this document can be implemented by using any kind of transistor known in the prior art. More specifically, bipolar junction transistors (BJTs) or field effect transistors (FETs) can be used in the differential cascode amplifier 100. All transistors used in the differential cascode amplifier 100 do not necessarily have to be of a same kind. However, an arbitrary combination of different types of transistors can be used.

In case that a BJT is used, a base port of the BJT can be regarded as a control port, an emitter port of the BJT can be regarded as an input port and a collector port of the BJT can be regarded as an output port.

In case that a FET is used, a gate port of the FET can be regarded as a control port, a drain port of the FET can be regarded as an output port and a source port of the FET can be regarded as an input port.

The cascode amplifier 100 can also be implemented using transistor types such as a heterojunction bipolar transistor (HBT), a darlington transistor, a schottky transistor, a multiple- emitter transistor, a dual gate MOSFET, a junction FET transistor, an avalanche transistor or a diffusion transistor.

A conventional differential cascode amplifier typically requires four transistors, two output loads, two DC voltage sources and one DC current source (as it is e.g. going to be described in view of Fig. 2 below). Fig. 1 however only shows those components of a differential cascode amplifier 100, which are required to achieve the core effect upon which the present invention is based, i.e. the tuning of the pass-band frequency response of the differential cascode amplifier 100. Any further components of the differential cascode amplifier, in particular those that are going to be described below, in particular in view of Fig. 2, can be regarded as optional features. Any variants of cascode differential amplifiers known in the prior-art are suitable to be used together with the present invention, in particular as described in view of Fig. 1.

Fig. 2 shows a differential cascode amplifier 200 according to an embodiment of the present invention in more detail. The differential cascode amplifier 200 as described below comprises all features and functionality of the differential cascode amplifier 100. All additional features and functionality of the differential cascode amplifier 200 can be considered as optional features. The features of Fig. 2 in particular relate to a cascode configuration of the differential cascode amplifier 200.

The differential cascode amplifier 200 specifically comprises a first voltage source 201, a first output port 202, a second output port 203, a first resistor 204, a second resistor 205, a second voltage source 206, a first common input port transistor 207, a second common input port transistor 208, a first current source 209, a first input port 210, and a second input port 211.

Moreover, the first common control port transistor 103 comprises a control port l03c, an input port l03i and an output port l03o.The second common control port transistor 104 comprises a control port l04c, an input port l04i and an output port 104o. The first common input port transistor 207 comprises a control port 207c, an input port 207i and an output port 207o. The second common input port transistor 208 comprises a control port 208c, an input port 208i and an output port 208o.

The respective components are connected to each other as it is illustrated in Fig. 2. In other words, the differential cascode amplifier comprises, as other prior art differential cascode amplifiers, four transistors 103, 104, 210 and 211 which can also be called Qi, Q 2 , Q3 and Q 4 ; two output loads 202 and 203, which can also be called RLI and RL2, two DC voltage sources 201 and 206, which can also be called VDD and VGG and one DC current source 209 which can also be called IE.

The differential input of the differential cascode amplifier can be represented by Vi n + and Vm- and can be delivered by ports 210 and 211.

The differential output of the differential cascode amplifier can be represented by V out+ and Vout- and can be applied to ports 202 and 203.

The two DC voltage sources 201 and 206, which can also be referred to as VDD and VGG, can also be provided by means of a single voltage source, from which both VDD and VGG can be tapped.

Fig. 3 shows schematic models of a transistor that can be used to analyze the behavior of the differential cascode amplifier 100 or 200 according to the present invention. The description of Fig. 3 in particular relates to all transistors of the differential cascode amplifier 100 or 200, except for transistors that are used to implement the first variable resistor 101 and/or the second variable resistor 102.

Although the functionality of the differential cascode amplifier 100 or 200 can be implemented by means of any kind of transistor, it is now demonstrated by using a known simplified model in which the transistors are assumed to be FETs, as shown in Fig. 3. In section A of Fig. 3 the correlation between the above described output, control and input ports of a general transistor and the drain, gate and source port of a FET is illustrated.

Section B of Fig. 3 shows an equivalent circuit of an FET composed by a voltage controlled current source (Ids = gm · V gs ) and two capacitors (C gs and C g d).

According to the equivalent circuit of the FET it can be demonstrated that a frequency bandwidth of a transfer function in cascode amplifiers is limited by common- source transistors, i.e. 207 and 208 in Fig. 2, and it has an upper pass-band frequency approximately located at the following frequency (f):

The above equation can be regarded as equation 1, in which Rs is an impedance of an input source and Zi n co is an input impedance of a common-gate transistor. The value of Zi n co can be estimated with the following equation (equation 2),

1 + li-2-

Z .inCG "

S.m +

in which it is assumed that the common-source transistors and common-gate, i.e. 103 and 104 in Fig. 2, transistors are equal, and thus resulting in the same values for components composing the equivalent model (g m , C gs and C gd ). Equation 1 and equation 2 show that the upper pass-band frequency of the differential cascode amplifier 200 depends on a value of the variable resistors 101 and 102. As a consequence, the pass-band frequency response of the differential cascode amplifier 200 can be tuned by tuning the value of the variable resistors 101, 102. Any asymmetry introduced in the differential cascode amplifier, both by the differential amplifier circuit (i.e. by Qi ¹ Q2 ¹ Q3 ¹ Q4 and/or R LI ¹ R L 2, respectively 103 ¹ 104 ¹ 210 ¹ 211 and/or 202 ¹ 203) and the variable resistors (R vari ¹ R var 2, respectively 101 ¹ 102) can change an actual behavior of the differential cascode amplifier 100 or 200, but does not affect the principle of operation on which the present invention is based.

Fig. 4 shows another differential cascode amplifier 400 according to an embodiment of the present invention. Two transistors 401 and 402 are inserted in the control port branch of the first common control port transistor 103 and the second common control port transistor 104. The two transistors 401 and 402 thus implement the variable resistors 101 and 102. The differential cascode amplifier 400 further comprises a control voltage source 403 that provides a control voltage to control the transistors 401 and 402, thereby further implementing the variable resistors 101 and 102. The embodiment shown in Fig. 4 is a preferred way to fully integrate the present invention in MMIC devices.

The configuration of the transistors composing the differential cascode amplifier (i.e. 103, 104, 210, 211) is the same as used in Fig. 2. Regarding the transistors 401 and 402, being FETs implementing variable resistors 101,102, their input and output terminals (i.e. their source and drain ports) are interchangeable. As a consequence, any combination of both input ports being connected to the first voltage source 201, both output ports being connected to the first voltage source 201 or one input port and one output port being connected to the first voltage source 201 are possible.

Fig. 5 shows another differential cascode amplifier 500 according to an embodiment of the present invention. The differential cascode amplifier 500 comprises all features and functionality of differential cascode amplifiers as described above. In the differential cascode amplifier 500, the variable resistors 101, 102 are implemented by means of potentiometers 501, 502.

Fig. 6 shows another differential cascode amplifier according to an embodiment of the present invention. The differential cascode amplifier 600 comprises all features and functionality of differential cascode amplifiers as described above. In the differential cascode amplifier 600, the variable resistors 101, 102 are implemented by means of switchable resistors 601, 602.

Although they are not shown in any one of Figs. 1 to 6, any combination of the first variable resistor of any of Figs. 1 to 6 and the second variable resistor any of Figs. 1 to 6 are possible. For example, the following combinations of first variable resistor 101 and second variable resistor 102 are also possible:

The first variable resistor 101 is implemented by beans of a transistor 401 and the second variable resistor 102 is implemented by means of a potentiometer 502.

The first variable resistor 101 is implemented by beans of a transistor 401 and the second variable resistor 102 is implemented by means of a switchable resistor 602. The first variable resistor 101 is implemented by beans of a potentiometer 501 and the second variable resistor 102 is implemented by means of a transistor 402.

The first variable resistor 101 is implemented by beans of a potentiometer 501 and the second variable resistor 102 is implemented by means of a switchable resistor 602.

The first variable resistor 101 is implemented by beans of a switchable resistor 601 and the second variable resistor 102 is implemented by means of a transistor 402.

The first variable resistor 101 is implemented by beans of a switchable resistor 601 and the second variable resistor 102 is implemented by means of a potentiometer 502.

Fig. 7 shows a schematic overview of a method 700 for operating a differential cascode amplifier 100 for optical communication that comprises a first variable resistor 101 connected to a second variable resistor 102, wherein the first variable resistor 101 is further connected to a control port l03c of a first common control port transistor 103 of the cascode amplifier 100 and the second variable resistor 102 is further connected to a control port l04c of a second common control port transistor 104 of the cascode amplifier 100. The method 700 corresponds to the differential cascode amplifier 100 of Fig. 1, and is accordingly for operating the differential cascode amplifier 100.

The method 700 comprises a step oftuning 701, by the first variable resistor 101 and the second variable resistor 102, a pass-band frequency response of the differential cascode amplifier 100.

The present invention has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed invention, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article“a” or“an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.