Description of the Related Art High-speed low voltage differential swing (LVDS) interfaces have become popular to use as display interfaces, especially for flat panel displays. By using an LVDS interface, the electromagnetic interference (EMI) level of computer systems may be sufficiently reduced to allow a computer system to pass current commercial EMI compliance limits. However, current commercial LVDS chip sets suffer from insufficient bandwidth; for example, many do not even have enough bandwidth to support XGA resolution, which is 455 Mbps (65 MHz x 7).

The main limitation on the required bandwidth is caused by timing skew. Skew is primarily caused by cable and board line length mismatches. The situation is aggravated as the cable length and the required bandwidth increases. Unless skew is properly corrected or managed, the required bandwidth cannot be met. Therefore, a skew-managing scheme for LVDS interface is needed which can remove the timing skew between data and clock channels, and thereby increase the maximum bandwidth of the system and enhance compatibility among LVDS chip sets.

SUMMARY OF THE INVENTION In accordance with the present invention, a skew-managing scheme for an LVDS system is disclosed to provide greater bandwidth for LVDS systems.

An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a delay locked loop, for converting

the LVDS clock signal into a full-swing clock signal, and a plurality of data recovery channels, each channel coupled to a data signal and comprising an LVDS converter, a skew adjust circuit, a sampler array, and a phase adjusting circuit. The delay locked loop and the data channel circuitry combine to remove skew from LVDS signals by generating multiple clock signals, sampling the data at multiple intervals, using the samples to eliminate skew, and retrieving correct data samples from the data signals.

In another embodiment, the sampler array comprises a plurality of transition sampling circuits, for sampling transitions between two adjacent serial bits of data and generating a lock signal and a sampled data signal responsive to the sampled transition, and a plurality of center sampling circuits, for sampling a center point of each serial bit of data and generating a center sample signal responsive to the sample, and the phase adjusting circuit for generating skew control signals responsive to the center sample signals, lock signals, and transition data signals received from the sampler array.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a block diagram of the skew-insensitive Low Voltage Differential Swing (LVDS) receiver.

Figure 2 illustrates timing diagrams of the skew removal operation of the receiver.

Figure 3 is a more detailed block diagram of the delay locked loop.

Figure 4 is a block diagram of the data channels.

Figures 5a-c are more detailed block diagrams of Tsampler and Xsampler circuits.

Figures 6a-c are timing diagrams illustrating the functionality of the phase adjusting circuit.

Figure 7 is a more detailed block diagram of the phase adjusting circuit.

Figures 8a-d are more detailed block diagrams of the components of the phase adjusting circuits.

Figure 9 is a more detailed block diagram of the skew-adjusting circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 illustrates the block diagram of the skew-insensitive Low Voltage Differential Swing (LVDS) receiver 100. The receiver 100 comprises a clock generating delay locked loop (DLL) 104, a threshold bias circuit 148, and four equivalent data recovery channels 126. The DLL 104 receives N MHz LVDS clock signals (RXC 127, RXCB 129)

from the cable and generates two sets of 7-phase N MHz clock (TCK (0: 6) 154, XCK (0: 6) 158).

Each data recovery channel 126 receives 7 x M Mbps LVDS serial data from the cable 132 and removes the skew between the clock 128 and the data 132 to recover 7-bit parallel data which is synchronized by the N MHz clock. For removing skew and accomplishing data recovery, each data recovery channel 126 uses the TCK (0: 6) 154, and XCK (1: 6) 158 generated by the DLL 104. The phase interval between two adjacent phase clock signals (TCK (n) to TCK (n+1), XCK (n) to XCK (n+1)) is equal to one bit time interval or a single data cycle. The phase interval between XCK (n) and TCK (n+1) is equal to a one-half bit time interval or a half-data cycle. In accordance with the skew-removing operation, described in greater detail below, transition clock signals XCK (1: 6) 158 continuously sample the transition position between the two adjacent serial bits, and center clock signals TCK (0: 6) 154 sample the exact center position of each serial bit. The 7-bit recovered data 108 is obtained by sampling the exact center positions of each serial bit using the rising edges of TCK (0: 6) 154.

As can be seen in Figure 2, the initial clock signals 128 are skewed with the initial data signals 132. Without correction, the clock signals 128 would cause the data 132 to be sampled to points other than the center point of each serial bit. This will lead to error, decreasing the maximum bandwidth. However, in accordance with the present invention, the skew between clock 128 and data 132 is corrected so that the maximum bandwidth can be maintained. The multiple sets of clock recovery signals TCK 154 and XCK 158 sample the bit streams at the transitions and the center points of the bits. The transition samples provides skew information. The center samples provide the output data 108.

Figure 3 illustrates the detailed block diagram of the DLL 104. The function of the DLL 104 is to generate multiple clock recovery signals 154,158 and a lock signal 150, after synchronizing all of the generated clock recovery signals 154,158. The DLL 104 comprises a differential-to-CMOS converter 336, a replica skew circuit 332, a replica skew bias circuit 340, a delay chain 304, a plurality of buffers 308, a phase detector 316, a charge pump 324, loop filter 328, and a lock detector 320. The differential-to-CMOS converter 336 receives the LVDS clock signal 127,129 (having differential amplitude) from the cable and converts it into a full swing clock signal (compatible with CMOS device operation). The converted full swing clock signal is transmitted to the replica skew circuit 332, which creates the exact same delay as a skew adjust circuit 404 in the initial state of each data channel 126 described below. The

replica skew bias circuit 340 continuously generates 0.5 Vdd, which determines the delay of the replica skew circuit 332. The replica skew circuit generates a reference delay, which provides a timing around which the actual skew is corrected. The output of the replica skew circuit 332, the delayed full-swing clock signal 305, is transmitted to the input of the delay chain 304.

The delay chain 304 comprises a plurality of delay devices 310. More specifically, the delay chain 304 comprises 14 delay devices 310. Each delay device 310 preferably comprises a delay cell 312 and a clock buffer 308; however, other methods of delaying a signal may also be used. XCK (0) is generated by passing the delayed full-swing clock signal 305 to the delay chain 304 through a clock buffer 308. The output of the 14th delay cell 312 generates XCK (7) 218 by passing the output of the 13th delay cell 312 through a clock buffer 308.

The phase detector 316 compares the rising edges of XCK (0) 204 and XCK (7) 218.

When the rising edge of XCK (7) 218 lags the rising edge of XCK (0) 204, the phase detector 316 generates an UP signal 317. When the rising edge of XCK (7) 218 leads the rising edge of XCK (0) 204, the phase detector 316 generates a DOWN signal 318.

Responsive to receiving an UP signal 317, the charge pump circuit 324 provides current into the loop filter 328 to increase control voltage of the delay chain 304, and thus reduce the total delay generated by the delay chain 304. When the charge pump circuit 324 receives a DOWN signal 318, the charge pump circuit 324 decreases as the amount of current from the loop filter 328 to decrease the control voltage and therefore increase the amount of delay generated by the delay chain 304. Thus, the loop filter 328 stabilizes the overall feed- back loop, and the rising edges of XCK (0) 204 and XCK (7) 218 are aligned, and equally spaced 14-phase clocks are obtained, as shown in Figure 2.

The lock detector 320 detects the lock-condition between XCK (0) 204 and XCK (7) 218 and generates DLL_LOCKB signal 322 in response. In one embodiment, when the rising edges of XCK (0) 204 and XCK (7) 218 are not aligned, the DLL_LOCKB signal 322 is"1"or high. After the rising edge of XCK (0) 204 and XCK (7) 218 are aligned, DLL_LOCKB signal 322 is"0"or low.

Figure 4 illustrates the detailed block diagram of a data recovery channel 126. The data recovery channel 126 comprises a differential-to-CMOS converter 402, a skew adjust circuit 404, a sampler array 424, a phase adjusting circuit 418 and an initial skew bias circuit 412. The differential-to-CMOS converter 402 converts LVDS serial data-in to full-swing data.

The converted full-swing data is transmitted to the skew adjust circuit 404. Normally, the skew adjust circuit uses TCK and XCK from the DLL to correct the skew. At the initial state, however, the DLL takes some time to reach lock-state until which TCK and XCK are unstable.

Before the DLL circuit 104 arrives at lock-state (i. e., while DLL-LOCKB is 1), the amount of delay generated by the skew adjust circuit 404 is controlled by the initial skew bias circuit 412.

On the initial state, the initial skew bias circuit 412 is activated and causes the skew control voltage 458 to be 0.5 x Vdd, which is the same as the replica skew bias voltage in the DLL circuit 104. As a result, on the initial state, the delay generated by the skew adjust circuit 404 in the data recovery channel 126 is equalized the delay generated by the replica skew circuit 332 in the DLL 104. The delay from RXO 131, RXOB 133 to DataIn 202 is therefore equal to the delay from RXC 127 RXCB 129 to XCK (0) 204. Thus, the cable skew between RXO 131, RXOB 133 and RXC 127, RXCB 129 is duplicated on the timing skew between DataIn 202 and XCK (0) 204 on the initial state. After the DLL 104 arrives at lock-state (DLL_LOCKB is '0'), the initial skew bias circuit 412 is disabled and the phase adjusting circuit 418 is activated to remove the skew between the clock and data path. On this active state, the skew adjust circuit 404 is controlled by the phase adjusting circuit 418 in each data recovery channel 126 and removes the skew between data and clock path.

The sampler array 424 preferably comprises seven Tsampler (TS (0: 6)) circuits 728, 730,732,734,736,738,740 and six Xsampler (XS (0: 6)) circuits 729,731,735,737,39 shown in more detail in Figure 7. A center sampling circuit, for example, Tsampler 728, samples the center position of each serial bit on the rising edge of a center clock signal 154 and generates a sample data Tout (n) 750 which then becomes the final recovered data. A transition sampling circuit, for example, Xsampler 729, samples the transition position between the two adjacent serial bits on the rising edge of XCK (n) and the transition clock signal 158 generates a sampled data Xout (n) and a no-phase-adjust signal, LOCK (n). When the Xsampler circuit 729 samples the exact transition position, LOCK (n) 754 becomes'1'and Xout (n) 752 is invalidated. When the transition clock signal 158 samples a position which is not the exact transition position, LOCK (n) 754 becomes'0'and Xout (n) 752 is validated and used by the phase adjusting circuit 418.

Figure 5 illustrates the detailed circuit diagrams of the Tsampler and Xsampler circuits. Figure 5a illustrates a Tsampler circuit 728,730,736,738,740 in more detail. The Tsampler (n) circuit comprises a single-phase clocking sense amplifier (SPCSA) 512, and two dual-state D-Flip Flop Circuits (DFF) 514. Figure 5c illustrates an embodiment of the SPCSA

512. When the clock signal 528 is low, transistors MPO and MP1 are turned on and act as the resistive load for the differential stage comprising transistors MNO, MN1, MPO, and MP1.

Transistors MN2 and MN3 are turned off to isolate the differential stage from the positive feedback circuit composed of transistors MP3 and MP4. Transistors MP2 is turned on to equalize the OUT and OUTB signals and to prepare for signal amplification. The differential data (DOUT, DOUTB) is developed on the differential stage according to the difference between DataIn 202 and the threshold voltage which is, in this case, ThM 166. When the clock signal 528 is HIGH, MPO, MP1 and MP3 are turned off. MN2 and MN3 are turned on and the positive feedback circuit comprising MP3 and MP4 amplifies the differential signal (DOUT, DOUTB) and creates the full swing sampled data (TOUT) 536. The middle threshold voltage ThM 166 used by Tsampler (n) is 0.5 Vdd, which is the ideal logic threshold for a full swing signal.

The Xsampler (n+1) circuit for sampling transitions is preferably composed of two SPCSAs 512,4 DFFs 514 and combinational logic. A first SPCSA 512 uses a low threshold voltage (ThL) 170 which is 0.33 Vdd. The output of the first SPCSA 512 and FlipFlop 514 is QL, a skew detecting signal. The other SPCSA circuit 513 uses a high threshold voltage (ThH) 62 which is 0.66 Vdd and generates through FlipFlop 514 an output QH, another skew detecting signal. If the XCK (n+1) signal 532 occurs close to the transition position of two adjacent serial bits (i. e., data and clock are aligned), the output of the first SPCSA 572, QL, is '1'and the output of the second SPCSA 572, QH, is'0'. The LOCK (n+1) signal 544 is'1'. If the XCK (n+1) signal is close the center position of the serial bit (i. e., data and clock are not aligned), the QL/QH outputs are 1/1 or 0/1, and the LOCK signal 544 is'0'. The threshold voltages, ThL, ThH, and ThM, are generated by the threshold bias circuit 148.

Figure 6 illustrates the operation of Tsampler and Xsampler in greater detail. Figure 6a shows the condition in which the data user and clock signals 204 are in exact alignment. In this condition, QH is'0'and QL is'1'because the sampled voltage level of the DataIn 202 is lower than 0.66 Vdd (the ThH threshold) and higher than 0.33 Vdd (the ThL threshold). As a result, the LOCK (n+1) signal transitions to'1'and XOUT (n+1) is invalidated. TOUT (n) and TOUT (n+1) samples the center position of each serial bit and become the recovered data.

Figure 6b shows the condition in which the data signal 202 leads the clock signal 204. In this condition the QH/QL outputs are 0/0 or 1/1 because the sample voltage level of the data is lower (or higher) than both of the levels of the ThH 170 and ThL 162 thresholds. As a result, LOCK (n+1) becomes'0'and XOUT (n+1) is validated. TOUT (n), XOUT (n+1), and

TOUT (n+1) are either 100 or 011, which causes the phase adjusting circuit 418 to assert a DOWN phase recommendation signal. Figure 6c shows the condition in which the data signal 20 lags the clock signal 204. In this condition, the QH/QL outputs are 1/1 or 0/0 because the sampled voltage level of the data is higher (or lower) than both the levels of the ThH and ThL thresholds. As a result, LOCK (n+1) signal becomes'0'and XOUT (n+1) is validated.

TOUT (n), XOUT (n+1), and TOUT (n+1) are either 110 or 001, which causes the phase adjusting circuit 418 to assert an UP phase recommendation signal.

Figure 7 illustrates a detailed block diagram of the phase adjusting circuit 418. In this embodiment, the phase adjusting circuit 418 comprises a phase detection logic circuit 720, a charge pump 716, and a loop filter 712. The phase detection logic circuit 720 is activated when DLLJLOCKB 322 becomes'0'. The phase detection logic circuit 720 receives Tout (0: 6) 750, Xout (1: 6) 752, and LOCK (1: 6) 754 and then determines the status of the skew between the data and clock path from the signals. When the data leads clock, the phase detection circuit 720 sets the UP phase recommendation signal 710 to'0'and the DOWN phase recommendation signal 711 to'1'. When data lags clock, the phase detection circuit 720 sets the UP phase recommendation signal 710 to'1'and the DOWN phase recommendation signal 711 to'0'. When the skew between the data and clock signals is completely removed, that is, data and clock are completely aligned, the phase detection logic circuit 720 sets the UP phase recommendation signal 710 to'0'and the DOWN phase recommendation signal 711 to'0'.

The charge pump 716 discharges the loop filter 712 to decrease the skew control voltage 458 and reduce the delay of the skew adjust circuit 404 when the UP phase recommendation signal 710 is'1'. The charge pump 716 charges the loop filter 712 to increase the skew control voltage 458 and increase the delay of the skew adjust circuit 404 when the DOWN phase recommendation signal 711 is'1'. Thus, skew between RXO 131, RXOB 133 and RXC 127, RXCB 129 which is duplicated on the timing skew between Dataln 202 and XCK (0) 204 is removed. As a result, TCK (0: 6) 154 continuously samples the exact center position of each serial bit and Tout (0: 6) 450 becomes recovered data. The Tout (0: 6) data signals 450 are synchronized by the TCK (0: 6) clock signals 154 respectively. After passing the paralleling FlipFlop 514 stage, Tout (0: 6) 450 becomes the final recovered data, Q (0: 6) 108, which is synchronized by TCK (2) 209.

Figure 8a is a more detailed illustration of the phase detection logic circuit 720. The phase detection logic circuit 720 preferably comprises six phase detection cells (PD Cell (0: 6))

840,844,848,856,860 and a stage for generating phase recommendation UP/DOWN pulses, as shown in Figure 8c. As shown in Figure 8b, PDCell (n) 864 receives the TOUT (n) 536, Xout (n+1) 540, LOCK (n+1) 544, and TOUT (n+1) 604 signals and generates an phase adjust signal UP (n) 876 and a phase adjust signal DOWN (n) 880 signals in response. As described above, when the data 202 and clock 204 signals are exactly aligned, the LOCK (n+1) signal 544 is 1, which causes the UP (n) and DOWN (n) signals 801,803 to be 0/0 respectively.

When data 202 leads clock 204, LOCK (n+1) 544 is'0'and the TOUT (n) 536, XOUT (n+l) 540, TOUT (n+1) 604 signals are 100 or 011, respectively, which causes the UP (n) and DOWN (n) signals 801,803 to be 0/1 respectively. When data 202 lags clock 204, the LOCK (n+1) 544 is'0'and TOUT (n) 536, XOUT (n+1) 540, TOUT (n+1) 604 are 110 or 001 respectively, which causes UP (n) and DOWN (n) signals 801 to be 1/0.

The UPF 884 and DOWNF 888 signals are obtained by ORing the UP (0: 5) 824,826, 828,830,832 and DOWN (0: 5) 825,827,829,831,833 signals together, respectively. The pulse generator 892 continuously generates pulses on every falling edge of the clock 204.

When DLL_LOCKB 322 is'1' (initial state), both the UP 877 and DOWN 878 pulses are set to'0', which disables the phase adjusting circuit 418 in the data recovery channel 126. When DLLJLOCKB 322 is'0' (active state), the pulse generator 892 are activated to activate the phase adjusting circuit 418 in the data recovery channel 126. When neither the UPF nor the DOWNF signals 884,888 are asserted, the UP/DOWN pulses 877,878 having the same pulse widths are asserted. When the UPF signal 884 is asserted and the DOWNF 784 is not, the width of UP pulse 877 becomes larger than that of DOWN pulse 878.

Figure 9 illustrates the skew adjust circuit 404 in each data recovery channel 126.

When DLL_LOCKB 322 is'0' (initial state), the phase detection logic circuit 720 is turned off, and both of the UP/DOWN pulses 877,878 are set to'0'as previously mentioned. As a result, the charge pump 716 goes into tri-state, the initial skew bias circuit 412 is activated, and the skew control voltage 458 is set to be 0.5 Vdd. Thus, the initial delay from RXO 131, RXOB 133 to DataIn 202 is equalized with the delay from RXC 127, RXCB 129 to XCK (0) 204. If timing skew caused by cable or board line length mismatches between RXO 131, RXOB 133 and RX 127, RXCB 129 exists, the same timing skew is duplicated between Dataln 202 and XCK (0) 204 on the initial state. When the DLL 104 acquires locking-state (DLL_LOCKB is 1 = Active state), the initial skew bias circuit 412 is turned off and goes into tri-state. The phase adjusting circuit 418 is activated and UP/DOWN pulses 877,878 are generated depending on initial timing skew between DataIn 202 and XCK (0) 204. The phase

adjusting circuit 418 back-adjusts the delay of skew adjust circuit 404 and removes the initial timing skew between clock and data channel so that TCK (0: 6) 154 correctly samples the exact center position of each serial bit 202 (DataIn).

While the invention has been described with reference to preferred embodiments, it is not intended to be limited to those embodiments. It will be appreciated by those of ordinary skill in the art that many modifications can be made to the structure and form of the described embodiments without departing from the spirit and scope of the invention, which is defined and limited only in the following claims. For example, the invention may be used to correct the skew between a high-speed data signal and an associated clock signal.