WU, Yue (11614 Chippenham Way, San Diego, California, 92128, US)
Claims:
! , A circuit comprising; a charge pump having a first output path outputting a first current and a second output path outputting a second current; a loop filter coupled to the charge puinp for filtering undcsircd signals, the loop filter comprising: a resistor coupled to the first output path, a first capacitor coupled to the first output path, and a second capacitor coupled to a second output path; and a voltage controlled oscillator (VCO) coupled to the loop filter, the VCO comprising; a first varactor having a gate coupled to the first output path and a drain coupled to the second output path, and a second varactor having a gate coupled to the first output path and a drain coupled to the second output path, wherein the second current is less than a first current by a ratio.
2. The circuit of claim 1, wherein the second output path is coupled to a node in between the drains of the first and second varactors.
3. The circuit of claim 2, wherein the capacitance of die first and second varactors is varied by varying the amount of first and second currents.
4. The circuit of claim 3, wherein the variance of the capacitance of the first and second varactors changes a frequency or a phase of an output signal of the VCO,
5. The circuit of clairø 4, wherein the VCO further comprises: a choke coupled io the first output path, first varactor and second \ aractor; and a third capacitor and an inductor coupled to the first and second varactors for determining a central frequency of the output signal of the VCO.
6. The circuit of claim 5, wherein the VCO further comprises: a first transistor and a second transistor cross coupled to each other for providing a positn c feedback that causes the oscillation of the output signal of the VCO.
7. The circuit of claim (\ further comprising: a phase detector thai determines a phase difference between a reference input signal and the output signal of the VCO, wherein the phase detector outputs a control signal to the charge pump which reSlects the phase difference.
8. The circuit of claim ?, wherein the charge pump varies the amount of the first and second currents based on the control signal.
9. fhc circuit of claim 8, further comprising a divider for dividing the frequency of the output signal of the VCO.
10. A circuit comprising. a charge pump a voltage controlled oscillator (VCO) coupled ϊo the loop filter, the VCO comprising: a first varactor having a gate coupled to the first output path and a drain coupled to the second output path, and a second varactor having a gate coupled to the first output path and a drain coupled to the second output path, wherein the second current is less than a first current by a ratio and wherein the second output path is coupled to a node in between, the drains of the first and second varactors.
1 1. The circuit of claim 10, wherein the capacitance of the first and second varactors is varied by varying the amount of first and second Currents, and wherein the first current and second current flow in opposite direction.
12. The circuit of claim I K wherein the variance of the capacitance of the first and second varactors changes a frequency or a phase of an output signal of the VCO,
13. The circuit of claim 12, further comprising: a phase detector that determines a phase difference between a reference input signal and the output signal of the VCO, wherein the phase detector outputs a control signal to the charge pump that controls the amount of the first current and the second current based on the phase difference. |
DIFFERING CHARGE PUMP CURRENTS FOR INTEGRATED PLL FILTER
[0001 J The present Application for Patent eiasms priority to Proiisionai Application
No 60 7X7,07X entitled ''A method to implementation of I 1 LL, dual path loop filter" filed March 28. 2006, and assigned to the assignee hereof and hereb} expressly incorporated by relerencc herein.
Field
|00021 The present disclosure relates generally to electronics, and more specifically lo a dual path loop {liter design for phase lock loop circuits
Background
|0003] Phase l ocked l oop (PI L) circuits are well known and used for frequency control in a variety of applications, l-or example, they can be configured as frcqucnc> multipliers, demodulators, tracking generators or clock recovery circuits. A typseal PLL crrcuit has a loop filter to filter out high frequency components such as spurs generated by a phase comparator or a charge pump in the PLL circuit. A typseal loop filter υsch passive components such as capacitors and resistors to filler out any undcsircd signals such as spurs. However, a typical loop iϊitcr requires high capacitance capacitorfs) to filter out high frequency components such as spurs. Since high capacitance capacitors occupy large amount of space in integrated circuits, the high capacitance capacitors could not be integrated into integrated circuits that include Pϊ I. circuits, As a result, the loop filters were usually located outside of the intcgtated circuits,
[0004! To solve the
acth e circuit components create additional noise and consume more power than passn e circuit components.
[0005J Therefore, there JS a need in the art for a new rj pc of dual path loop filter design that can ameliorate the shortcomings of previous loop filter designs.
SUMMARY
S(KJUo] A PLL circuit is described herein. In an embodiment, the PLL circuit include** a charge pump that has a first output path and a second output path Each of the output paths output a current signal such that the current from the second output path is less than the current from the first output path by a ratio. The PLL further includes a loop fϋier coupled io the charge pump for filtering out undesired signals Mich as spurs. The loop filler includes a resistor and a capacitor coupled to the first output path and another capacitor coupled to a second output path. The PLL circuit also includes a
(0007 j Various aspects and embodiments of the imcπtions arc described in further detail below .
BRIF.F DESCRIPTION OF THE DRAWINGS
{0008} Die features and nature of the present ind ention will become more apparent from the detailed description set forth below v\ heu taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.
|000*>| Fig. 1 shows a block diagram of a PLL circuit.
[0010} Fig. 2 shows a detailed circuit diagram of the PLL cireuu.
DETAILED DESCRIPTION
[OOϊJ j The word "'exemplary" is used herein to mean "serving as an example, instance, or illustration," Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
J(HM 2 j Fig. \ shows a block diagram of a PLL circuit 100 in accordance with an embodiment. A phase detector 101 receives a reference input signal at an input 104. The reference input signal may be a local oscillator signal produced by a local oscillator in a receiver or may be any other type of signal that the PLL circuit 100 is tracking. An input 103 of the phase detector 101 receives an output from a divider 120 that reduces the frequency of the output signal, from a voltage controlled oscillator (VCO) 1 15. The phase detector 101 determines a phase difference between the reference input signal and the output signal from the divider 120 and produces an output based on the phase difference. The output from the phase detector 101 is a voltage signal that is proportional to the phase difference and controls the charge pump 105. The charge pump 105 receives the output from the phase detector 103 and outputs a differential/dual current signal that is proportional to the phase difference,
[00 Oj A dual path loop filter 1 10 receives the differential current output from the charge pump 105 and filters out any undesired signals such as spurs. The VCO 1 15 receives the output from the filter 1 10 and outputs a signal with a frequency and/or phase controlled by the input signal, from the filter 1 1.0. Basically, the frequency /phase of the output signal from VCO 1 15 is altered in. response to the phase difference detected by the phase detector 101. The divider 120 receives the output signal from the VCO ! 1.5 and divides the frequency of the signal received from the VCO 1 15, The divider 120 outputs the frequency divided signal to the phase detector 101 , Thus, the
phase deieeior i θl , charge pump 105, filter 1 10, VCO 1 15 and dh idcr 120 form a
feedback loop to track and lock the output of the VCO 1 15 lo the reference input signal.
[(KM 4| Fig. 2 shows the PLL circuit K)O in more detail Specifically, Fig. 2 shows the circuitry for the dual path loop filler 1 10 and the VCO 1 15 in detail. The filter 1 S O includes a resistor R i and capacitors Cl and C4 The VCO 1 15 includes a choke L S , varactors CV1 and CV2, capacitors CO, C2 and C3, an inductor LO. a current source CS I and transistors S l and S2.
10015] As described abo\ c. the charge pump S 05 has a diffcrefUJaϊ''dual output with an output path 106 and an output path 107. As shown in Fig 2, the resistor R I and the capacitor Cl arc coupled between the output path 106 and the ground, and the capacitor C-4 is coupled betw een ihc output path S 07 and the ground, Slie output path 10ft is coupled to the choke I 1 , and one end of the choke I i is coupled Io a gale of the \araetor CV 1 and the other end is eoupied to the gate of the \araclor C V2. The output path 107 is coupled to the drains of the
jOOiό} The capacitance of
[0θ!7j The chaigc pump 105 is designed such that the output path 106 outputs a current
of value I and the output path 107 outputs a current of value — where B ^ 1 (the value
of B w ill be explained in detail below ), and the current flow direction is opposite to each
other (e.g., if current i flow s toward the VCO 1 15, then current Hows into the
R
charge pump 105.) Assume that Zl = impedance of RI and Cl together and Z2 = the
impedance of C4, then CVgd = (I ♦ Zl ) - {- ■»» * Z2) = 1 * Zl -h ! * ZI since the choke
B B
Ll acts aa a short circuit in low frequency. The previous equation shows that the capacitance of the varactors CVl and CV2 is controlled by the amount of current 1 and
, Since the phase difference between the reference input signal and the output
signal from the VCO 1 i 5 controls the amount of current i outputled by the charge pump 105, the phase difference controls the capacitance of CV! and CV2.
[00 IS) The inductor LO and capacitor CO determine the central output frequency of the
VCO 1.15, but the capacitance of the varactors CVl and CV2 is varied to vary the output frequency of the VCO 1 15 as shown fay the following equation:
1 1 1 φ (] _ C- }
" ™ ^ ~ ^^ ~ VIO * CO " 2C0-
where C v — the total capacitance of CV 1 and CV2, OJ ~ the output frequency of the VCO 115,
O CVgd, thus ω «CVgd.
fOQϊ9| Furthermore, as stated above, the output path 107 outputs a current of value
where B > 1. The value for * 7i" is chosen such that the capacitance of C4 is reduced
to a point where the capacitor C4 can be integrated into the main JC circuit that includes the FLL circuit SOO, As explained above, in a conventional PLL circuit, the capacitance of a capacitor forming a part of a loop filter is so large that the capacitor cannot be integrated into the main IC circuit and must be external to the main IC circuit. However, in a PLL circuit in accordance with an embodiment, the capacitance of C4 is smaller by a factor of B in comparison to a capacitor in a loop filter of a conventional PLL- circuit. By carefully choosing a valise for S, the capacitance of capacitor C4 can be reduced so that the capacitor C4 can be integrated into the main 1C circuit. Thus,
the structure of the PLI. circuit 100 allows the dual path loop filter NO to be formed without using a large capacitor that must be external to the mam 1C circuit and allow s the dual path loop filter 110 to be formed without any acU\c circuit elements that may cause additional noise and increase power consumption.
[0020] The capacitors C2 and C 3 are coupled to the gates of the ^araetors CVl and
CV2 and act as AC coupling capacitors that isolate any DC" path to the gates of the varaciors CVl and CV2 (e.g , prtrvent the short of VDD to the gates>) The transistors SI and S2 are cross coupled to each other so that they provide posithe feedback to each other to cause and maintain oscillation. 4 current source CS ! is coupled to the drains of the transistors Sl and S2 and to the ground, as shown in Fig, 2.
[0021] Tiic PI I. circuit described herein ma) be used for \ariout> communication
Sj StCnK For example, the PI l circuit may be used for Code Division Multiple Access (CDMA) systems. Tune DJMSIOπ Multiple Access { TDMyV) systems, I-rcqucnc} Division Multiple Access (I- DMA) systems. Orthogonal Frequency Drusion Multiple Access (OH)MA) systems, multiple-input multiple-output (MIMO) systems, w ireless local area networks (LANs), and so on. λ C 1 DMA system may implement a radio access technology (RAT) Mich as Wideband CDMA (W-COMA). edma200ϋ, and so on. RAT refers to the technology used for over-thc-air communication. A TDMA system may implement a RλT such as Global System for Mobile Communications (GSM). Universal Mobile Telecommunication System (UM TS) is a system that u^es W-CDMA and GSM as R ATs. The PLL circuit may also be used for various frequency bands such as, for example, a cellular band from 824 to H 94 MI i/, a Personal Communication S\siem (PCS) band fiora 1850 to WO MHA a Digital Cellular System (DCS) baud from 1710 to 18S0 MK/, an International Mobiic TeScconirøunieations-2000 (IM T- 2000) band from 1920 to 2170 MH/, and so on.
[0022] The PLJ.. circuit described herein may be implemented within an integrated circuit (IC), an RF integrated circuit (RFIC), an application specific integrated circuit (ASIC), a printed circuit hoard U 5 CB), an electronic device, and so on. The PLL circuit may also be fabricated with various 1C process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (N-MOS), P- charcnei MOS (P-MOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiCk*), gallium arsenide (GaAs), and so on, f0023J The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the ait τ and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.