**DIGITAL AUTO FREQUENCY CONTROL FOR A GENERAL PURPOSE IF SUBSYSTEM WITH MULTI-MODULATION SCHEMES**

*;*

**H04L27/00***;*

**H04B1/06***;*

**H04B15/00***;*

**H04L27/06***;*

**H04L27/14**

**H04L27/22**US7593692B2 | 2009-09-22 | |||

US20100239051A1 | 2010-09-23 | |||

US6606487B2 | 2003-08-12 |

CLAIMS What is claimed is: 1. A method for automatic frequency control (AFC) comprising: monitoring a received strength signal indicator (RSSI) signal; when the RSSI signal exceeds a predetermined threshold, calculating a moving average of binary elements of the received signal; and continuing the step of calculating the moving average until the AFC converges. 2. The method in accordance with Claim 1 wherein the step of calculating the moving average comprises calculating the moving average of the binary elements of the signal without demodulating the signal. 3. The method in accordance with Claim 2 further comprising an adaptive tracking loop gain scheme utilizing multiple estimations of a carrier frequency offset (CFO) estimation. 4. The method in accordance with Claim 3 wherein the adaptive tracking loop gain scheme comprises: estimating the CFO; adjusting a loop gain in response to the estimated CFO; and repeating the estimating and adjusting steps until accurate tracking is achieved. 5. The method in accordance with Claim 4 further comprising normalizing in-phase (I) and quadrature (Q) signal samples to estimate the CFO. 6. The method in accordance with Claim 5 further comprising the step of calculating the RSSI signal in response to the I and Q signal samples, and wherein the step of normalizing the I and Q signal samples comprises normalizing the I and Q signal samples in response to the RSSI signal. 7. The method in accordance wit Claim 6 wherein the step of normalizing the I and Q signal samples comprises normalizing the I and Q signal samples by bit shifting the I and Q signal samples. 8. The method in accordance with Claim 6 wherein the step of normalizing the I and Q signal samples comprises normalizing the I and Q signal samples by truncating the I and Q signal samples. 9. An automatic frequency control (AFC) device comprising: an input module for down converting and sampling a received signal; a received signal strength indicator (RSSI) module coupled to the input module and calculating a RSSI signal in response to the down converted and sampled received signal; and a carrier frequency offset (CFO) estimation module coupled to the input module and the RSSI module for calculating a moving average of binary elements of the down converted and sampled received signal when the RSSI signal exceeds a predetermined threshold, the CFO estimation module continuing to calculate the moving average until the AFC converges. 10. The AFC device in accordance with Claim 9 wherein the CFO estimation module receives an undemodulated received signal from the input module, the CFO estimation module calculating the moving average of the binary elements of the signal without demodulating the undemodulated received signal. 11. The AFC device in accordance with Claim 0 further comprising an adaptive loop filter coupled to the CFO estimation module for performing an adaptive tracking loop gain utilizing multiple estimations of the CFO from the CFO estimation module. 12. The AFC device in accordance with Claim 11 wherein the adaptive loop filter has two operational modes and switches between the operational modes in response to the estimations from the CFO estimation module. 13. The AFC device in accordance with Claim 11 wherein the adaptive loop filter repeatedly performs the adaptive tracking loop gain in response to an estimated CFO signal received from the CFO estimation module until accurate tracking is achieved. 14. The AFC device in accordance with Claim 11 further comprising a normalization module for normalizing in-phase (I) and quadrature (Q) signal samples, the normalization module coupled to the CFO estimation module for providing the normalized I and Q samples to the CFO estimation module to estimate the CFO. 15. The AFC device in accordance with Claim 14 wherein the RSSI module calculates the RSSI signal in response to the I and Q signal samples, and wherein the normalization module normalizes the I and Q signal samples in response to the RSSI signal. 16. The AFC device in accordance with Claim 15 wherein the normalization module normalizes the I and Q signal samples by bit shifting the I and Q signal samples. 17. The AFC device in accordance with Claim 15 wherein the normalization module normalizes the I and Q signal samples by truncating the I and Q signal samples. |

PRIORITY CLAIM

[0001] The present application claims priority to Singapore Patent Application No. 201301351-1, filed 22 February, 2013.

FIELD OF THE INVENTION

[0002] The present invention generally relates to digital automatic frequency calibration (AFC) circuits, and more particularly relates to a digital AFC circuit for use in a general purpose intermediate frequency (IF) subsystem with multi- modulation schemes.

BACKGROUND

[0003] Many wireless channel digital frequency and phase modulation systems such as frequency shift keying (FSK), Gaussian frequency shift keying (GFS ), and minimum phase shift keying (MSK) are sensitive to carrier frequency offset (CFO) caused by transceiver oscillator instability and/or Doppler shift. This is especially true when data is transmitted in a burst mode. One possible solution applies an auto- frequency calibration (AFC) block in the receiver to automatically estimate and compensate for such frequency offset. However, compared with the multiplicity of conventional designs for FSK/GFSK/MSK transceivers, CFO estimation and compensation circuits for such systems are rare.

[0004] Conventional CFO estimation and/or compensation schemes have many drawbacks. An early conventional scheme utilized a set of analog AFC tracking algorithms and can be recognized as the basis of the modern digital AFC. Some conventional digital schemes utilized a set of digital closed-loop decision-aided AFC tracking algorithms for GFSK systems. However, both of these algorithms require reconstruction of transmitted data symbols and submission of these data symbols to the CFO estimator as reference information. Therefore, the trackable AFC range of these conventional schemes is limited so as to not exceed the maximum frequency divination and, thus, accurate sample timing recovery is required. Another typical scheme utilizes an open-loop AFC tracking algorithm which directly estimates the DC offset of the discriminator output. However, application of this AFC algorithm is limited to frequency modulation systems with discriminator demodulators. A direct CFO estimator based on received signals and remodulated transmitted symbols has also been proposed, but the channel response and the training sequence must be known in advance. Further, some conventional AFC algorithms are based on Fast Fourier Transforms (FFT) and Maximum Likelihood which have disadvantageous high computational requirements.

[0005] Additionally, many of the existing AFC algorithms assume that the received signal has a constant envelope. However, this assumption is not always true, especially when the Inter-Channel Interference (ICI) and Automatic Gain Control (AGC) uncertainties are taken into account. A further normalization method for AFC in GFSK systems normalizes the estimated CFO to the maximum deviation, ignoring gains along the receiving path..

[0006] Thus, what is needed is an easy to implement automatic frequency calibration scheme which does not require timing recovery and/or source data recovery while also taking into account the ICI and AGC uncertainties. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.

SUMMARY

[0007] According to the Detailed Description, an automatic frequency control (AFC) device is provided. The AFC device includes an input module, a received signal strength indicator (RSSI) module, and a carrier frequency offset (CFO) estimation module. The input module down converts and samples a received signal. The RSSI module is coupled to the input module and calculates a RSSI signal in response to the down converted and sampled received signal. The CFO estimation module is coupled to the input module and the RSSI module and calculates a moving average of binary elements of the down converted and sampled received signal when the RSSI signal exceeds a predetermined threshold. The CFO estimation module continues to calculate the moving average until the AFC converges.

[0008] In accordance with another aspect, a method for automatic frequency control (AFC) is provided. The method includes monitoring a received strength signal indicator (RSSI) signal and calculating a moving average of binary elements of the received signal when the RSSI signal exceeds a predetermined threshold. The method further includes continuing the step of calculating the moving average until the AFC converges.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to illustrate various embodiments and to explain various principles and advantages in accordance with a present embodiment.

[0010] FIG. 1 depicts a block diagram of an intermediate frequency (IF) subsystem utilizing an automatic frequency calibration (AFC) circuit in accordance with a present embodiment.

[0011] FIG. 2 depicts a graph of discriminator output of normalized I and Q channel samples comparing discriminator output with a normalized input in accordance with the present embodiment to discriminator output with a non-normalized input.

[0012] FIG. 3 depicts a flowchart of the operation of the normalization scheme of the AFC circuit depicted in FIG. 1 in accordance with the present embodiment.

[0013] FIG. 4 depicts a graph of tracking logs of the AFC circuit of FIG. 1 at different settings in accordance with the present embodiment.

[0014] FIG. 5 depicts a graph of a comparison of convergence speeds of the AFC circuit of FIG. 1 at different settings in accordance with the present embodiment.

[0015] And FIG. 6 depicts a graph of a comparison of root mean square errors of tracking results of the AFC circuit of FIG. 1 at different settings in accordance with the present embodiment.

[0016] Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been depicted to scale. For example, the dimensions of some of the elements in the block diagrams or flowcharts may be exaggerated in respect to other elements to help to improve understanding of the present embodiments. DETAILED DESCRIPTION

[0017] The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description. It is the intent of the present embodiment to present a novel non-decision-aided digital closed loop automatic frequency control (AFC) tracking algorithm based on the moving average of the digital discriminator's output. This AFC does not require timing recovery arid/or source data recovery. While existing decision-aided AFC methods usually require received data to be demodulated even before CFO is compensated thereby limiting the tracking range to below the maximum frequency deviation, the AFC in accordance with the present embodiment does not have such a requirement and thus has a wider tracking range. An adaptive tracking loop gain scheme is also proposed to achieve a faster and more accurate tracking. The scheme automatically switches between fast and accurate modes by adjusting the loop gain according to the estimated CFO for each iteration. Lastly, Inter-Channel Interference (ICI) and Automatic Gain Control (AGC) uncertainties are also taken into consideration by normalizing the in-phase (I) and quadrature (Q) samples by re-using the existing digital RSSL Meanwhile, the normalization is based on a simple bit shift and truncation process which makes it easy to implement.

[0018] Referring to FIG. 1, a block diagram 100 of a continuous-phase frequency shift keying (CPFSK) modulation device in accordance with a present embodiment is depicted. While the block diagram 100 and the discussion of the AFC algorithm in accordance with the present embodiment is limited to a CPFSK modulation device, the present embodiment and its AFC algorithm is applicable to any frequency modulation scheme including FSK, GFSK, and MSK. It will also be clear to those skilled in the art that the present embodiment based on a general CPFS system can be easily applied to other phase modulation schemes.

[0019] Assume the received CPFSK signal is not distorted by channel and pre- detection filter, it can be denoted as

*( = jf½ cos(27r/ _{c }t + 0(t) + 0 _{O }) + n(t) (1) where fc is the carrier frequency, n(t) is an additive bandpass Gaussian noise with one-sided power spectrum density No, -¾ and T _{b } are the bit energy and bit period respectively. It should be noted that E _{b } is the bit energy with the effects of AGC and with ICI removed by low-pass filter. It varies with different AGC or different ICI. θο is the initial phase offset and 6{t) is the frequency modulated phase as shown below

where g(t) is the pulse shaping function for binary data, and h is the modulation index.

[0020] The block diagram 100 presents a device for closed-loop recursive automatic frequency calibration (AFC) algorithm for CFO estimation/compensation. The received waveform is received by an input module 1 10 which down converts the signal x(f) (Equation 1) to produce baseband in-phase (I) and quadrature (Q) signals. Ignoring the noise, the signals can be expressed as

/(t) = JJjJ cos(27t4/t + 0(t) + 0p) (3)

^{Q ( ) = } J¾ sin(2 ^{7 }r4/t + Θ (t) + 0 _{O }) (4) where Af = f _{c } - / _{c }' is the frequency offset, and / _{c }' is the frequency generated by the local oscillator. [0021] The input module 110 then samples the I(t) and Q(f) signals at a sampling rate \IT _{S } and then normalized by a normalization module 1 12. The normalized samples are then passed to a digital discriminator 1 14 of a carrier frequency offset (CFO) module 116. The delay taps of the digital discriminator 114 are set to D and the discriminated signal is filtered by a low pass filter (LPF) 118. Thereafter, a moving average block 120 with window size L _{w } generates an indication of the difference between the transceiver's carrier frequency offset Af. Lastly, the error signal is filtered by a loop filter module 122 to smooth out the noise and is used to steer a phase lock loop (PLL) to generate a frequency of a local oscillator 124 towards

[0022] From FIG. 1, it can be imagined that the error signal is proportional to the gains along the receiving path including AGC adjustment and low-pass filter for removing ICI. It is necessary to remove or suppress such correlation by normalization. A received signal strength indication module 126 provides a RSSI signal to the normalization module 112 for normalization by reusing the digital RSSI signal.

[0023] The over-sampled version of the complex baseband signals given by Equations 3 and 4 can be written as

[0024] These I Q samples are passed to the discriminator 114 for further operation. However, the discriminator 114 output is proportional to the overall gains along the receiving path. Thus, the estimated CFO signal output from the CFO module 116 necessarily includes a constant ambiguity which needs to be removed. In accordance with the present embodiment, the normalization module 112 directly normalizes the I Q samples before they are fed to the discriminator 114. This advantageously narrows the required dynamic range of the digital discriminator 114 and achieves a stable tracking speed. In addition, reusing of the RSSI signal from the RSSI module 126 saves power consumption and chip area. In the digital RSSI module 126, the signal power is estimated by a filter 128 filtering an average value of the powers of I Q samples calculated by block 130, i.e.,

P = i ^{2 } V< + Q ^{2 }ik] (7) where L _{R } is the length of the observation window of the RSSI. The estimated signal power is mapped to dB with resolution of 1 dB at a gain to dB block 132 and fed to the normalization module 112 to normalize the I Q samples. The normalization module 112 performs a dividing operation by truncating and shifting the fixed point samples. As each integer value of RSSI corresponds to a number of bits and direction of I Q samples (fixed-point numbers) that are to be shifted and the shifted numbers are truncated in accordance with the normalization requirements, the normalization module 112 shift and truncation process is easily implemented. Furthermore, the I Q samples are normalized within a certain range so that the AFC will never loose convergence, given other necessary conditions are satisfied.

[0025] Referring to FIG. 2, a graph 200 illustrates the output of the digital discriminator 114 when the input I Q samples are normalized in accordance with the normalization scheme of the present embodiment. The I Q sample signal power is plotted along the x-axis 202 and the mean square value of the output of the discriminator 114 is plotted along the y-axis 204. The power of the input signal spans from 0 to 60 dB (normalized to Vpp = IV). Without normalization (trace 206) the discriminator output increases as the I Q signal power increases. However, after normalization, it is clear that the discriminator 114 output is limited in a reasonable range as seen in the bounded saw-blade pattern of trace 208.

[0026] The digital discriminator 114 outputs are the normalized I Q samples. Substituting this output into Equation 2 can be expressed as

± /[fc - D fc] - /[fc]<? [fc - D]

= sin {2nAfDT _{s } + [9(kT _{s }) - 9(kT _{s } - DT _{S })]}

= sin [2nAfDT _{s } + 2nh \ } x[n]g( - ηΤ)άτ}

= sin {2n[LfDT _{s } + W(kT _{s })]}

(8) where 0(kT _{s }) is defined by

[0027] For the average of the above discriminator 114 output ξ[£] with an observation window size being L _{w } samples, if the preamble satisfies the condition of (0,1) balance in the observation window, then the average output can be expressed as

I[k - D]Q [k] - I[k)Q[k - D] n{2n[AfDT _{s } + h0(kT _{s })]}

L _{w }+l-l

= ~ {sm(2nAfDT _{s }) Y cos[2nh0( kT _{s })]

+ cos(2nAfDT _{s }) sin[27r/i0(fcr _{s })]}

k=l

(10) [0028] Under the condition of the preamble being (0,1) balanced, it can be proven that the first summation term of Equation 10 in the big bracket can be approximated by a positive constant, and the second summation term approximately equals zero, that is

^ ^{1'1 } cos[2nhQ(kT _{s })] « a (11)

Σ^ΐΐ ^{'1 } sin[2nh0(kT _{s })] = 0 (12)

Therefore in view of the above and taking the AWGN noise into consideration, the moving average calculated at the block 120 and in Equation 10 can be rewritten as ξ » - sin(27TA Z ^{) }r _{s }) + w(n) = 2πβ^ΌΤ _{5 } + w'(n) (13) where w{n) refers to the effect of AWGN noise, and w '(n) is the overall noise including the approximation error. Thus, the frequency offset output from the CFO module 1 16 can be estimated by

[0029] The approximation in Equation 13 holds only when 2πΔ/Ε ^{) }Γ _{ί } is small. But when the feed-back tracking loop of the module 122 is employed, the condition for the loop to converge is that s (2 AflDT _{s }) has the same sign as Af to prevent the estimation of CFO being tracked to a wrong direction. Therefore, the condition of convergence is \2 AfiDT _{s } | < π, that is

-≡F _{s } ^{< Af < } _{s } ^{(15) }

[0030] The structure of the tracking loop filter 122 with adaptive gain is based on a standard feedback loop except that the loop gain in the loop filter 122 is adaptive to achieve fast tracking speed as well as accuracy. Since the parameter β in Equation 14 would be affected by factors such as sample timing error, a closed-loop recursive method is implemented to avoid this problem. The overall gain 1/(2πβ£Τ _{ί }) is absorbed into the loop gain K _{p } and it should be noted that K _{p } has a certain range of tolerance for tracking convergence. Hence the tracking speed and accuracy is not very sensitive to the error of the parameter β.

[0031] The loop filter 122 has two working modes, a Fast Mode and an Accurate Mode. It automatically switches between these two modes according to the absolute value of the moving average ξ[&] for each iteration as shown in FIG. 1. A positive threshold ζ is preset. The tracking loop is switched to Fast Mode or Accurate Mode if

|ξ[£]| is detected above or below ζ, respectively. The mode switching is achieved by selecting High or Low values of the loop gain K _{p }. It is set to a high value Kh in the Fast Mode, and set to a low value Ki in the Accurate Mode, where Kh and Ki are preset for each system.

[0032] In noisy cases, it is possible that jumps between above ζ and below ζ, respectively, for some consecutive iterations. To avoid such gain oscillation, the mode switching can be limited to happen only when is stabilized after switching from one side of the threshold to another. FIG. 3 depicts a flowchart 300 illustrating the logic of this gain control. At step 302, ξ[&] is received and at step 304 it is detected whether is above or below ζ. When |ξ[¾| is above ζ 304, the logic operates in the Fast Mode and it is decided 306 whether the previous ξ[£] (i.e.,

- l j) is greater than ζ, i.e., whether the operating mode is already in the Fast

Mode. If operation is already in the Fast Mode 306, the counter is incremented 308 and it is determined 310 whether the number of samples is equal to the observation window size, that is whether the counter equals L _{c }. If operation is not in the Fast Mode 306, the counter is initialized to zero 312 and it is determined 310 whether the counter equals L _{c }. When the counter equals L _{c } 310, the number of samples is equal to the observation window size and the loop gain K _{p } is set equal to the high value K _{h } 314 in the Fast Mode and the signal is filtered by multiplying by K _{p } 316.

[0033] Alternatively, when is below ζ 304, the logic operates in the

Accurate Mode and it is decided 318 whether the previous (i.e., is higher than ζ, i.e., whether the operating mode is in the Fast Mode. If operation is in the Fast Mode 318, the counter is initialized to zero 320 and it is determined 322 whether the counter equals L _{c }. If operation is already in the Accurate Mode 318, the counter is incremented 324 and it is determined 322 whether the number of samples is equal to the observation window size, that is whether the counter equals L _{c }. When the counter equals L _{c } 322, the number of samples is equal to the observation window size and the loop gain K _{p } in the Accurate Mode is set equal to the low value Ki 326 and the signal is filtered by multiplying by K _{p } 316.

[0034] The following Table 1 shows the comparison of the main features of the AFC circuit of FIG. 1 and conventional AFC implementations.

Parameters Present 1 ^{st } Prior Art 2 ^{nd } Prior 3 ^{rd } Prior Art 4 ^{th } Prior Art Embodiment Art

IF 172.8 MHz 8MHz 8MHz N.A. 910 MHz

Data Rate 1.2-4.8MHZ 3MHz 3MHz 0.7-2.1MHz . 1MHz

Over 9x 8x 8x N.A. 4x Sampling

Converge 16 bits >32 bits >32 bits - N.A.. _{. } N. A. Speed

Mod Multi GFS GFSK GFSK GFSK

Dec- Aid No Yes Yes - N.A. No

Norm Yes No No Yes No

Adaptive Yes No No No No Gain

Trackable ±4.5 ±0.033 ±0.033 N.A. ±0.24 kflRb

Residual Δ/ 2.4% 3.0% 3.5% N.A. 3.9% SNR=10dB

TABLE 1

[0035] From the contents listed in Table 1 , it can be concluded that the AFC algorithm in accordance with the present embodiment has attractive features in the areas of tracking speed, accuracy, and trackable range. The normalization scheme by reusing the existing digital RSSI and the shifting/truncating-based process to fixed point samples maintains balance between the performance and system complexity. The I Q samples are normalized to within a certain range by simple MSB searching, bit shifting and truncation. Further, the non-decision-aided CFO estimation algorithm can advantageously achieve a wider trackable range because the CFO is estimated by the moving average of the discriminator outputs and does not require timing recovery nor need to reconstruct transmitted symbols. In this manner, CFO estimation in accordance with the present embodiment has no limitation for its tracking range to be less than the maximum frequency deviation. The trackable CFO range is identified mathematically in Equation 15, above, and the advantages of this feature are proven by the contents listed in Table 1. Also, by automatically switching the adaptive loop gain between High and Low values according to the estimated CFO for each iteration, the loop gain is switched between Fast and Accurate modes, advantageously providing a higher tracking speed and better performance.

[0036] Referring to FIG. 4, a graph 400 depicts the AFC tracking results for the present embodiment of FIG. 1 with and without adaptive gain control and two different observation window length (18 and 36) are considered. The number of samples (i.e., time) is plotted along the x-axis 402 and the frequency is plotted along the y-axis 404 where the target CFO frequency is shown by the true CFO trace 406. It can be observed that the convergence speed of the system with adaptive gain control (traces 410, 414) in accordance with the present embodiment to the true CFO 406 is faster than that with constant loop gain (traces 412, 416). The graph 400 also shows the effects of the observation window length on the tracking speed. On one hand, the larger the window size 36 (traces 412, 414), the higher the estimation accuracy. On the other hand, the larger window size also slows down the tracking speed. Therefore estimation accuracy and tracking speed has to be balanced.

[0037] Referring to FIG. 5, a graph 500 depicts the convergence rate where signal- to-noise ratio (SNR) is plotted along the x-axis 502 and the number of samples needed to converge is plotted along the y-axis 504. It can be seen from the graph 500 that the adaptive gain simulations (traces 506, 508) take less samples to converge than constant gain (traces 510, 512).

[0038] Lastly, in FIG. 6, a graph 600 depicts the tracking performance of the proposed AFC with different settings where SNR is plotted along the x-axis 602 and Root Mean-Square (RMS) Error is plotted along the y-axis 604. The adaptive gain simulations are plotted on traces 608, 612 and the constant gain simulations are plotted on traces 606, 610. The performance of a prior art decision-aided AFC is also simulated for comparison on trace 614. In graph 600 it is shown that the proposed algorithm (traces 608, 612) achieves better performance than the decision-aided algorithm 614. This is because the performance of the decision- aided AFC 614 depends on the accuracy of timing recovery. Given the fact that there exists some random timing error, decision-aided AFC necessarily suffers some performance degradation.

[0039] Thus, in accordance with the present embodiment, an advantageous, robust moving average based AFC tracking algorithm has been presented which overcomes the drawback of the prior art. This algorithm is an easy to implement AFC scheme which does not require timing recovery and/or source data recovery and also takes into account the ICI and AGC uncertainties. The present embodiment can be applied to any CPFSK systems. The carrier frequency offset is estimated in the CFO module 116 by averaging at the block 120 the digital discriminator 1 14 output. An adaptive tracking loop with auto-switching loop gain is provided by the loop filter 122 to achieve higher tracking speed and accuracy. In addition, a simple normalization scheme with the assist of the existing digital RSSI 126 by shifting and truncation is provided to narrow down the required dynamic range the digital discriminator 114 and remove the effects of inter-channel interference and AGC uncertainties. The automatic loop gain control scheme is a simple comparing and switching process which is valuable to further optimize the threshold and the values of High and Low gains. While exemplary embodiments have been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. For example, those skilled in the art will realize from the teachings herein that the present technology may also be applied to any frequency modulation scheme including FSK, GFSK, and MSK.

[0040] It should further be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, operation, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements and method of operation described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims.

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