DIGITAL CONTROL OF BRIDGELESS POWER FACTOR CORRECTION

CIRCUIT

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to Provisional Application Serial No. 60/626,117 filed November 8, 2004, entitled DIGITAL CONTROL OF BRIDGELESS POWER FACTOR CORRECTION CIRCUIT, the entire disclosure of which is hereby incorporated by reference herein. The present application further claims benefit of and priority to Provisional Application Serial No. 60/675,541 filed April 28, 2005 entitled DIGITAL IMPLEMENTATION OF PFC, the entire disclosure of which is also incorporated by reference herein.

[0002] This application is also related to Provisional Application Serial No. 60/626,113 filed November 8, 2004 entitled PWM BLANKING ALGORITHM IN HIGH-FREQUENCY PARTIAL PFC, Provisional Application Serial No. 60/626,112 filed November 8, 2004 entitled DC BUS VOLTAGE CONTROL METHOD IN HIGH-FREQUENCY PARTIAL PFC and U.S. Patent Application No. 11/165,939 filed June 24, 2005 entitled HIGH FREQUENCY BOOST POWER FACTOR CORRECTION CONTROL CIRCUIT AND METHOD which claims the benefit of and priority to Provisional Application Serial No. 60/583,752 filed June 28, 2004 entitled A NEW HIGH-FREQUENCY PARTIAL BOOST POWER-FACTOR- CORRECTION CONTROL METHOD, the entire disclosures of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

[0003] The present invention relates to power factor correction circuits, that is, circuits for reducing the distortion and harmonics generated in a power line feeding a power supply, and in particular a switched mode power supply to make the circuit, 2 ₃ 9.1

including the attached load, appear to be a substantially resistive load. More specifically, the present application relates to a control circuit for use in digital control of a bridgeless power factor correction (PFC) circuit. The aim of power factor correction circuits is to ensure that the AC voltage and current are substantially in phase which improves efficiency and at the same time eliminates the generation of harmful harmonics.

[0004] In a conventional boost power factor correction circuit such as that illustrated in Fig. 1, it is common to use a rectifying bridge as illustrated. The rectified AC is provided to the boost inductor Ll. A PFC switch Ql is coupled in series with the inductor and across the output of the bridge rectifier after the inductor. The boost diode BD is coupled in series with the inductor Ll and the output capacitor COUT is coupled as shown at the output of the boost converter circuit in known fashion. The voltage across the capacitor COUT comprises the DC bus voltage which is provided to a load which might comprise, for example a DC to AC inverter driving a three phase motor load ML, for example.

[0005] The boost converter circuit is typically controlled via a control circuit in the manner illustrated in Fig. 2. The output of the DC bus Vdc is provided to an A to D converter 10 which has as inputs the DC bus voltage Vdc, the current I _1N in the inductor Ll as sensed by a resistor Rl or by other sensing means, as well as the rectified AC input voltage V _1N . The A to D converter produces three outputs comprising digital implementations of the DC bus voltage, VdcFdb, the input voltage V_IN and the inductor current I_IN.

[0006] A ramp generator 20 receives a DC target voltage VdcTgt. The output of the ramp generator is provided to a difference circuit 22 in which the DC bus voltage is subtracted from the ramp voltage. This is fed to a voltage regulator which may comprise a PI controller 24. The output of the PI controller 24 is fed to a multiplier circuit 26 wherein the voltage output from the voltage regulator (PI controller) and the input voltage VJQNT are multiplied. This results in a reference PFC

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signal IREF PFC 28, from which the inductor current is subtracted in a difference stage 30. The output of this difference stage 30 is fed to a current regulator 32 comprising a PI controller. The output of the controller 32 is fed to a comparator 34 wherein the PWM signal is generated by comparing an oscillator signal typically a ramp or sawtooth signal 36 generated by an oscillator with the output of the controller 32. This controls the duty cycle of the PWM signal provided to control the switch Ql and thereby control the power factor correction.

[0007] The traditional boost power factor correction circuit, utilizing the bridge rectifier, however, has some drawbacks and thus it is often advantageous to utilized a bridgeless power factor correction circuit such as that illustrated in Figure 3, for example. It is noted that in the bridgeless PFC only two devices are in series in each current flowing path, thus reducing total forward voltage drop, conduction losses and improving efficiency of the circuit. In addition, since two IGBT' s Ql, Q2 are utilized, the thermal stress on each is reduced by 50%. These features have lead to an increased use of bridgeless PFC circuits in motor drive applications, such as air conditioners for example.

[0008] The control of bridgeless PFC circuits, however, has not developed quickly. In fact, the utilization of digital control circuits for controlling bridgeless PFC circuits has been unknown until now. One of the challenges to the control of the bridgeless PFC circuits is how to sense the input AC line voltage to provide a sinusoidal reference to shape the PCF current. The PFC control circuit needs a rectified half-sinusoidal AC voltage signal which refers to the negative DC bus voltage as ground. Li the conventional PFC circuit, the rectified half sinusoidal AC voltage is ' available as a result of the use of the bridge rectifier. Naturally, this half sinusoidal AC voltage is not available in the absence of the bridge rectifier.

[0009] While some solutions have been proposed to solve this problem, such as the use of an additional isolation transformer and an additional diode bridge rectifier, or the use of an opto-coupler and an additional processing circuit to obtain a zero

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crossing point of the input AC line voltage, these solutions add significantly to cost and the complexity of the circuit.

[0010] An aim of the present invention is to provide a digital control circuit for use with a bridgeless PFC circuits that avoids the problems noted above.

SUMMARY OF THE INVENTION

[0011] The invention provides an alternative PFC circuit and method that uses a differential operational amplifier with offset voltage to scale down the bi-polar AC input voltage of the PFC to uni-polar AC voltage, with the uni-polar AC voltage digitized and then processed in the digital domain to remove the offset provided by the operation amplifiers and to provide absolute values of the digital data in order to provide a half-sinusoidal AC signal that is proportional to and in phase with the input AC line voltage.

[0012] A circuit for providing power factor correction includes a bridgeless boost converter circuit and a control circuit receiving an input AC line voltage of the bridgeless boost converter circuit, wherein the control circuit provides a pulse width modulated signal to control the on time of a PFC switch of the bridgeless boost converter circuit The control circuit includes a scaling device operable to scale down a bi-polar AC voltage of the input AC line voltage to a uni-polar AC voltage, an analog to digital converter operable to convert the uni-polar AC voltage into digital data and a digital rectifier operable to process the digital data of the uni-polar AC voltage to provide a half-sinusoidal AC signal that is proportional to and in phase with the input AC line voltage for use in providing the pulse width modulated signal.

[0013] A method for providing power factor correction in a bridgeless boost converter circuit includes receiving an input AC line voltage of the bridgeless boost converter circuit, scaling a bipolar AC voltage of the input AC line voltage down to provide a uni-polar AC voltage, converting the uni-polar AC voltage into digital data, processing the digital data of the uni-polar AC voltage to provide a half sinusoidal AC

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voltage signal that is proportional to and in phase with the input AC line voltage and generating a pulse width modulated signal to control an on time of a PFC switch of the bridgeless boost converter circuit, wherein the sinusoidal AC voltage signal is used to generate the pulse width modulated signal.

[0014] A control circuit for use with a bridgeless boost converter circuit to provide power factor correction includes an input operable to receive an input AC line voltage of the bridgeless boost converter circuit, a scaling device operable to scale down a bi-polar AC voltage received from the input AC line to a uni-polar AC voltage signal, an analog to digital converter operable to convert the uni-polar AC voltage into digital data, a digital rectifier operable to process the digital data of the uni-polar AC voltage to provide a half-sinusoidal AC signal that is proportional to and in phase with the input AC line voltage and a pulse width modulated signal generator operable to provide a pulse width modulated signal to control an on time of a PFC switch of the bridgeless boost converter circuit, wherein the half sinusoidal AC signal provided by the digital rectifier is used to provide the pulse width modulated signal.

BRIEF DESCRIPTION OF THE DRAWING(S)

[0015] The invention will be now be described in greater detail in the following detailed description with reference to the drawings in which

[0016] Fig. 1 shows a conventional boost converter circuit;

[0017] Fig. 2 shows a control circuit in conjunction with the boost converter circuit of Fig. 1;

[0018] Fig. 3 shows a bridgeless boost converter circuit;

[0019] Fig. 4 illustrates a bridgeless boost converter circuit with a digital control circuit in accordance with a preferred embodiment of the present invention;

[0020] Fig. 5 shows waveforms in the circuit of Fig. 4;

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[0021] Other objects, features and advantages of the present invention will be apparent from the following detailed description.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0022] With reference to the drawings, Fig. 3 illustrates a bridgeless boost converter circuit 30. The bridgeless boost converter circuit 30 is includes inductors Ll and L2 is series with each lead of the input AC line. Diodes Dl and D2 are placed in series with the inductors Ll and L2, respectively. Switches Ql and Ql, which are preferably IGBT transistors are placed in parallel with the diodes Dl and D2 respectively. The diodes Dl and D2 act as boost diodes and the output capacitor COUT is coupled as shown at the output of the bridgeless boost converter circuit in a known fashion. The voltage across the capacitor COUT comprises the DC bus voltage which is provided to a load which might comprise, for example a DC to AC inverter driving a three phase motor load ML.

[0023] Figure 4 illustrates a power factor correction circuit in accordance with a preferred embodiment of the present invention. The circuit includes bridgeless boost converter circuit 30 and a digital control circuit 40 which may be used to control the bridgeless boost converter circuit 30. Converter circuit 30 is substantially the same as that described above with respect to Fig. 3.

[0024] The input AC line voltage, comprising Vac_l and Vac_2, of the bridgeless booster converter circuit 30 is provided to a differential operational amplifier 41 of the digital control circuit 40 via resistors Rl and R2. The gain of the operational amplifier 41 is provided by the following equation:

VacJN = R3/R1+R2 • (Vac_l-Vac_2) + V offset

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where Yoffset is approximately 0.6 V when the analog-to-digital converter (ADC) 42 utilized by the control circuit has an input range of 0-1.2V. The capacitors Cl, i.e. the ones across the operational amplifier, reduce high frequency common mode grounding noise. The capacitors C2 reduce differential mode noise. The operational amplifier 41 scales the bi -polar input AC line voltage, which may have a peak of up to 380 V, down to provide a uni-polar AC voltage Vac_IN, which preferably has an amplitude compatible with the ADC 42, such as 1.2 V. The uni-polar AC voltage of the operational amplifier VacJN is then provided to the ADC 42 where a digital implementation of Vac_IN signal, VaC-IN ¹ ' is provided . While in the preferred embodiment, a differential operational amplifier with voltage offset is used to scale down the input AC line voltage, any scaling device that receives the bi-polar AC voltage of the input AC line voltage and provides a scaled down uni-polar AC voltage signal may be used.

[0025] The digital data related to the uni-polar AC voltage VaC-IN ¹ from the ADC 42 is provided to a digital rectifier 43. The digital rectifier 43 removes the offset voltage provided by the operational amplifier 41 and provides absolute values for the digital data related to the unipolar AC voltage, V _{30 1N} ¹ , to provide a half sinusoid AC signal, Vac_Ctrl that is proportional to and in phase with the input AC line voltage.

[0026] As noted above, the uni-polar AC voltage signal Vac_IN is provided to the ADC 42. In addition, the output of the DC bus V _dc is also provided to the ADC 42 along with the current IJN as sensed by a resistor RI, or by other sensing means. The ADC 42 produces three outputs comprising digital representations of: the DC bus voltage, VdcFdb (VdcFdb ¹ ), the unipolar AC voltage, VacJN (VaC-IN ¹ ) and the current LIN (I-IN ¹ ).

[0027] The digital representation of the DC reference voltage (VdcFdb ¹ ) is provided to a difference circuit 44 in which the digital implementation of the DC bus voltage (VdcFdb ¹ ) is subtracted from a DC reference voltage Vdc_Ref . This result is fed to a voltage regulator, which may comprise a PI controller 45. The output, VAOut, 39.1

of the PI controller 45 is fed to a multiplier circuit 46 wherein it is multiplied with the half sinusoidal AC signal Vac_Ctrl. This results in a reference PFC signal I Ref, from which the current I_IN is subtracted in a difference stage 47. The output of this difference stage 47 is fed to a current regulator 48 comprising a PI controller. The output of the controller 48, VcPFC is fed to a PFC Pulse Width Modulation generator (PFCPWM) 49 wherein the PWM signal is generated to control the duty cycle of the PWM signal provided to control the switches Ql and Q2 and thereby control the power factor correction.

[0028] As can be seen by the above description, the control circuit operates in substantially the same manner as it would with a booster converter circuit with a rectifier bridge except for the scaling of the input AC line voltage and the processing of the digital data related to the scaled signal to remove the effects of the scaling and to provide the half sinusoidal AC signal. Once generated, the half sinusoidal signal is treated in much the same manner as the rectified voltage is when utilizing a booster converter circuit with a rectifier bridge.

[0029] Fig. 5 shows signals in the circuit of Fig. 4 including the DC bus voltage, the AC input voltage and the AC input current and the PFC Inductor current illustrating that the circuit of Fig. 4 provides effective control of power-factor correction.

[0030] It is noted that the circuits of Fig. 3 or Fig. 4 may be implemented in integrated circuit form in a single package if desired.

[0031] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore the present invention should be limited not by the specific disclosure herein, but only by the appended claims.

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