Title:
DIGITAL ENGINEERING METHOD AND PROCESSOR OF THE MIXED Q N-ARY AND CARRY LINE
Document Type and Number:
WIPO Patent Application WO/2004/092946
Kind Code:
A1
Abstract:
The present invention relates to the field of digital engineering method and processor, it provides a new digital engineering method, improves operational speed. The mixed Q N-ary and carry line of digital engineering method according to the present invention includes: A digital sign is added to every bit of the common Q N-ary digitals participating in the operation , there are k mixed N-ary digitals to participate in the operation. Sums up k mixed Q N-ary at the same time. Adding by bit beginning with the lowest bit, i. e., at a certain bit, two digitals of the above described k digitals are taken and added to generate 'addition by bit”, and the sum is taken into the next operation layer as “partial sum', meanwhile the acquired 'mixed digital carry' is put into the high-order bit which is close to the bit that is any carry line of the next operation layer. The operations don't stop until it generates 'mixed Q N-ary carry' line. Then the sum obtained by the last 'addition by bit' is the result if addition operation. The present provides a processor with mixed Q N-ary and carry line operation.
Inventors:
LI ZHIZHONG (CN)
XU JUYUAN (CN)
XU JUYUAN (CN)
Application Number:
PCT/CN2004/000375
Publication Date:
October 28, 2004
Filing Date:
April 19, 2004
Export Citation:
Assignee:
LI ZHIZHONG (CN)
XU JUYUAN (CN)
XU JUYUAN (CN)
International Classes:
G06F7/48; (IPC1-7): G06F7/00
Foreign References:
| US6073149A | 2000-06-06 | |||
| CN1136680A | 1996-11-27 |
Attorney, Agent or Firm:
CHINA PATENT AGENT(H.K.) LTD. (Great Eagle Centre 23 Harbour Roa, Wanchai Hong Kong, CN)
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