Title:
DIGITAL PHASE COMPARATOR AND METHOD
Document Type and Number:
WIPO Patent Application WO/2010/032830
Kind Code:
A1
Abstract:
A digital phase comparator of high resolution is provided without increasing the circuit area and the power consumption. A delay circuit array (21_1 to 21_n–1) generates delayed signals (CKC(1) to CKC(n–1)) obtained by delaying an input signal (CLK2) by equal intervals. Hold circuits (22_1 to 22_n) use the delayed signals (CKC(1) to CKC(n–1)) to sample an input signal (CLK1). An OR circuit (24) outputs OR of output signals of the hold circuits (22_1 to 22_n) as FCLK1. A delay circuit array (11_1 to 11_n–1) generates delayed signals (DC(1) to DC(n)) obtained by delaying CLK1 by equal intervals. Hold circuits (23_1 to 23_n) use the delayed signals (DC(1) to DC(n)) to sample CLK2. An OR circuit (25) outputs OR of output signals of the hold circuits (23_1 to 23_n) as FCLK2. A delay circuit array (51_1 to 51_m) generates delayed signals (DF(1) to DF(m)) obtained by delaying FCLLK1 by equal intervals. A delay circuit array (52_1 to 52_m) generates delayed signals (CKF(1) to CKF(m)) obtained by delaying FCLLK2 by equal intervals that are different from the delay time intervals of the delay circuit array (51_1 to 51_m). Hold circuits (53_1 to 53_m) use the delayed signals (CKF(1) to CKF(m)) to sample the respective delayed signals (DF(1) to DF(m)). Hold circuits (12_1 to 12_n) use CLK2 to sample CLK1 and the delayed signals thereof (DC(1) to DC(n–1)). Sampling results (QC(1) to QC(n)) of the hold circuits (12_1 to 12_n) and sampling results (QF(1) to QF(m)) of the hold circuits (53_1 to 53_m) are outputted to logic circuits (1, 5), respectively, as values corresponding to the phase difference between CLK1 and CLK2.
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Inventors:
TOKAIRIN TAKASHI (JP)
MAEDA TADASHI (JP)
KITSUNEZUKA MASAKI (JP)
MAEDA TADASHI (JP)
KITSUNEZUKA MASAKI (JP)
Application Number:
PCT/JP2009/066381
Publication Date:
March 25, 2010
Filing Date:
September 18, 2009
Export Citation:
Assignee:
NEC CORP (JP)
TOKAIRIN TAKASHI (JP)
MAEDA TADASHI (JP)
KITSUNEZUKA MASAKI (JP)
TOKAIRIN TAKASHI (JP)
MAEDA TADASHI (JP)
KITSUNEZUKA MASAKI (JP)
International Classes:
H03K5/26; H03L7/085
Foreign References:
| JP2008160594A | 2008-07-10 | |||
| JP2008104148A | 2008-05-01 |
Attorney, Agent or Firm:
KATO, Asamichi (JP)
Asamichi Kato (JP)
Asamichi Kato (JP)
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