Title:
DIGITAL PHASED ARRAY ARCHITECTURE AND ASSOCIATED METHOD
Document Type and Number:
WIPO Patent Application WO2001067548
Kind Code:
A3
Abstract:
Digital phased array architecture and associated method are disclosed that eliminate the necessity of utilizing analog phase shifters in the receive and transmit signal paths. Desired delays are instead generated by adjusting the timing of sampling signals sent to analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) in the receive and transmit signal paths.
Inventors:
FRAZIER GARY A
Application Number:
PCT/US2001/006734
Publication Date:
March 07, 2002
Filing Date:
March 02, 2001
Export Citation:
Assignee:
RAYTHEON CO (US)
International Classes:
H01Q3/26; H01Q3/30; H01Q3/38; (IPC1-7): H01Q3/26
Foreign References:
| US5943010A | 1999-08-24 | |||
| US4688045A | 1987-08-18 | |||
| US5130717A | 1992-07-14 |
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