Title:
DIGITAL SIGNAL PROCESSING METHOD AND DEVICE AND PROGRAMMABLE LOGIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/019196
Kind Code:
A1
Abstract:
A digital signal processing method and device and a programmable logic device, relating to the field of digital circuits, and used for solving the existing problem in the prior art that the use of a fixed bit-width multiplier might result in low resource utilization and inferior operation performance. The invention comprises K multipliers (201), a shift control circuit (202), and a selection control circuit (203). The ith multiplier of the K multipliers (201) is used for performing multiplication with a bit width of Mi bits as a multiplicand and a bit width of Ni bits as a multiplier. The shift control circuit (202) is connected to the K multipliers (201), and is used for receiving K products outputted by the K multipliers (201), and for performing shift control processing on the K products to obtain K processed products and outputting the K processed products to the selection control circuit (203). The selection control circuit (203) is connected to the shift control circuit (202), and is used for receiving the K processed products sent by the shift control circuit (202) and outputting a result of accumulating the K processed products or outputting the K processed products.
Inventors:
YANG WEIGUO (CN)
PAN JIANFENG (CN)
CHEN XIUBO (CN)
PAN JIANFENG (CN)
CHEN XIUBO (CN)
Application Number:
PCT/CN2017/095061
Publication Date:
January 31, 2019
Filing Date:
July 28, 2017
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F7/523
Foreign References:
| CN104133655A | 2014-11-05 | |||
| CN106528046A | 2017-03-22 | |||
| CN106484366A | 2017-03-08 | |||
| US4872128A | 1989-10-03 |
Attorney, Agent or Firm:
BEIJING ZBSD PATENT & TRADEMARK AGENT LTD. (CN)
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