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Title:
DIGITAL-TO-ANALOG CONVERTER CIRCUIT WITH TWO ENCODING SCHEMES
Document Type and Number:
WIPO Patent Application WO/2018/133927
Kind Code:
A1
Abstract:
The disclosure relates to a digital-to-analog converter (DAC) circuit (100), comprising: a plurality of conversion cells (103), each conversion cell (103) comprising a pair of subcells (110, 120), each subcell (110) comprising a current source (111) and a switch (112) which is configured to switch the corresponding current source (111) to an output (113) of the subcell (110); and a digital encoder (105), configured to generate a digitally encoded output signal (106) for controlling the switches (112, 122) of the pair of subcells (110, 120) of the conversion cells (103), wherein the digital encoder (105) is configured to selectively generate the digitally encoded output signal (106) according to a first encoding scheme (101) or according to a second encoding scheme (102).

Inventors:
VANDENAMEELE, Patrick (Munich Bayern, 80992, DE)
VATTI, Sofia (Munich, 80992, DE)
SAMSOM, Johannes (Munich, 80992, DE)
CORNELISSENS, Koen (Munich Bayern, 80992, DE)
STYNEN, Paul (Munich, 80992, DE)
ROVERATO, Enrico (Taavetinaukio 3 B 18, Helsinki, 00300, FI)
KOSUNEN, Marko (Rantakartanontie 8, Helsinki, 00910, FI)
RYYNÄNEN, Jussi (Latvakuja 2, Vantaa, 01400, FI)
Application Number:
EP2017/050944
Publication Date:
July 26, 2018
Filing Date:
January 18, 2017
Export Citation:
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Assignee:
HUAWEI TECHNOLOGIES CO., LTD. (Huawei Administration Building Bantian Longgang District, Shenzhen, Guangdong 9, 518129, CN)
VANDENAMEELE, Patrick (Munich Bayern, 80992, DE)
International Classes:
H03M1/74
Foreign References:
US20140253357A12014-09-11
US20110273317A12011-11-10
US20070252739A12007-11-01
Other References:
None
Attorney, Agent or Firm:
KREUZ, Georg (Huawei Technologies Duesseldorf GmbH Riesstr. 8, Munich, 80992, DE)
Download PDF:
Claims:
CLAIMS:

1 . A digital-to-analog converter (DAC) circuit (100), comprising: a plurality of conversion cells (103), each conversion cell (103) comprising a pair of subcells (110, 120), each subcell (110) comprising a current source (111 ) and a switch

(112) which is configured to switch the corresponding current source (111 ) to an output

(113) of the subcell (110); and a digital encoder (105), configured to generate a digitally encoded output signal (106) for controlling the switches (112, 122) of the pair of subcells (110, 120) of the conversion cells (103), wherein the digital encoder (105) is configured to selectively generate the digitally encoded output signal (106) according to a first encoding scheme (101 ) or according to a second encoding scheme (102).

2. The DAC circuit (100) of claim 1 , wherein the first encoding scheme (101 ) is a fully differential encoding scheme, and wherein the second encoding scheme (102) is a pseudo-differential encoding scheme.

3. The DAC circuit (100, 200) of claim 1 or 2, wherein each conversion cell (103) is configured to adopt a ternary output state comprising a high state, a low state and a zero state when the second encoding scheme (102) is selected, wherein the ternary output state is based on a switching state (201 , 202, 203, 204) of the switches (112, 122) of the conversion cell (103).

4. The DAC circuit (100, 200) of claim 3, wherein each conversion cell (103) is configured to adopt only two of the three output states at any given time.

5. The DAC circuit (100, 200) of claim 3 or 4, wherein each conversion cell (103) is configured to: generate a positive output signal (113, 123) when a first subcell (110) of the conversion cell (103) is turned on (204) and a second subcell (120) of the conversion cell (103) is turned off (201 ), generate a negative output signal (113, 123) when the first subcell (110) is turned off (203) and the second subcell (120) is turned on (202), and generate a zero output signal (113, 123) when both subcells (110, 120) of the conversion cell (103) are turned off (203, 201 ). 6. The DAC circuit (100, 200) of one of the preceding claims, wherein the digital encoder (105) is configured to turn on always one and only one subcell (110) of a conversion cell (103) when the first encoding scheme (101 ) is selected.

7. The DAC circuit (100, 200) of claim 6, wherein each conversion cell (103) is configured to adopt a differential output state comprising a high state and a low state when the first encoding scheme (101 ) is selected, wherein the differential output state is based on a switching state (201 , 202, 203, 204) of the switches (112, 122) of the conversion cell (103).

8. The DAC circuit (100, 200) of claim 7, wherein each conversion cell (103) is configured to: generate a positive output signal (113, 123) when a first subcell (110) of the conversion cell (103) is turned on (204) and a second subcell (120) of the conversion cell (103) is turned off (201 ), and generate a negative output signal (113, 123) when the first subcell (110) is turned off (203) and the second subcell (120) is turned on (202). 9. The DAC circuit (100, 200) of one of the preceding claims, wherein a first subcell (110) of the pair of subcells (110, 120) comprises a first current source (111 ) configured to generate a first current; and wherein a second subcell (120) of the pair of subcells (110, 120) comprises a second current source (121 ) configured to generate a second current, wherein a total output current at the DAC circuit is formed by adding contributions from all the first current sources (111 ) of the first subcells (110) and subtracting

contributions from all the second current sources (121 ) of the second subcells (120).

10. The DAC circuit (100, 200) of one of the preceding claims, wherein each subcell (110, 120) comprises a first transistor forming the switch (112, 122) and a second transistor forming the current source (111 , 121 ). 11. The DAC circuit (100, 200) of one of the preceding claims, comprising: a controller configured to control the digital encoder (105) selecting the first encoding scheme (101 ) or the second encoding scheme (102).

12. The DAC circuit (100, 200) of claim 11 , wherein the controller is configured to control the digital encoder (105) based on linearity and/or power requirements. 13. The DAC circuit (100, 200) of claim 11 or 12, wherein the controller is configured to set part of the conversion cells (103) to zero, in particular during backoff.

14. The DAC circuit (100, 200) of one of the preceding claims, wherein the digital encoder (105) is configured to selectively generate the digitally encoded output signal (106) according to a third encoding scheme in which each conversion cell (103) is configured to simultaneously adopt a high state, a low state and a zero state.

15. A digital transmitter circuit, comprising: a modulator circuit, configured to modulate a radio signal to provide a digital input signal; and a DAC circuit (100, 200) according to one of the preceding claims, configured to convert the digital input signal to an analog output signal (113, 123).

Description:
Digital-to-Analog Converter circuit with two encoding schemes

TECHNICAL FIELD

The present disclosure relates to a Digital-to-Analog Converter (DAC) circuit, in particular a Radio Frequency DAC circuit, with two encoding schemes. The disclosure further relates to a digital transmitter, in particular an all-digital RF transmitter including such a DAC circuit. The disclosure particularly relates to a method to dynamically trade off linearity and power efficiency in digital transmitters.

BACKGROUND

RF-DACs (Radio Frequency Digital to Analog Converters) are one of the most important building blocks of digital transmitters. RF-DACs are implemented using conversion cells which can be resistors, capacitors or more commonly switches and current sources (called current steering RF-DACs). These conversion cells are arbitrarily weighted according to the application requirements and their number increases with increase in the number of system bits or resolution. The RF-DAC is implemented and used in one hardware configuration that is either tuned to be power efficient with the disadvantage of reducing linearity or tuned to be high linear with the disadvantage of improved power consumption.

SUMMARY

It is the object of the invention to provide a hardware design for a digital-to-analog converter (DAC), in particular an RF-DAC, providing flexibility between high linearity and low power consumption requirements. This object is achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

A basic idea of the invention is to use a digital encoder that produces a digital encoded output, capable of supporting two encoding schemes, such as fully differential and pseudo differential encoding schemes, by controlling the switches in such a way that they can be turned on or off according to the encoding scheme implementation of the RF-DAC. This gives the freedom to choose between the first, e.g. fully differential or the second, e.g. pseudo differential RF-DAC within the same single hardware implementation according to the dynamically changing linearity and power consumption needs. The disclosed approach solves the limitation of mutually exclusive hardware implementation of fully differential and pseudo differential RF-DACs.

Fully differential RF-DACs always keep all the conversion cells turned on whereas pseudo differential RF-DACs have the ability to turn certain conversion cells off if their contribution to the output is not needed. The two encoding schemes represent a trade-off between power and linearity. The fully differential scheme has the advantage of being more linear but consumes more power when compared to the pseudo differential scheme, which has the disadvantage of being relatively less linear but consumes lesser power. One of the reasons the implementation of fully differential and pseudo differential RF- DACs on a single hardware sharing arrangement is useful is the power and linearity tradeoff between the two. In the fully differential RF-DAC the output is more linear, however the RF-DAC is quite power consuming as compared to the pseudo differential RF-DAC. The power saved in pseudo differential RF-DAC is dependent on the input signal used, and is found to be equal to the PAPR (Peak-to-Average Power Ratio) for a full-scale input signal.

This disclosure resolves the above described implementation limitation and presents a DAC circuit and a method to implement both the fully differential and pseudo differential RF-DACs in a single hardware sharing implementation. Since the hardware requirements are same for both the implementations, as will be evident shortly, the idea here is to modify the digital encoding process before the RF-DAC in such a way that the RF-DAC can accommodate both the fully differential and pseudo differential types.

This hardware sharing implementation of RF-DACs is desirable because it gives the ability to dynamically change requirements on linearity according to the application needs without changing any hardware.

For the sake of simplicity and understanding, in the following description only current steering RF-DACs are considered. So any reference to the RF-DACs or their conversion cells will be meant for current steering structure unless otherwise specified. Of course, the concept described hereinafter can be applied to any other hardware platform

implementing RF-DACs.

In order to describe the invention in detail, the following terms, abbreviations and notations will be used:

RF: Radio Frequency

DAC: Digital-to-Analog Converter

PAPR Peak-to-Average Power Ratio

INL: Integral Nonlinearity

ACLR Adjacent Channel Leakage Ratio

LTE: Long Term Evolution

According to a first aspect, the invention relates to a digital-to-analog converter (DAC) circuit, comprising: a plurality of conversion cells, each conversion cell comprising a pair of subcells, each subcell comprising a current source and a switch which is configured to switch the corresponding current source to an output of the subcell; and a digital encoder, configured to generate a digitally encoded output signal for controlling the switches of the pair of subcells of the conversion cells, wherein the digital encoder is configured to selectively generate the digitally encoded output signal according to a first encoding scheme or according to a second encoding scheme.

Such a DAC circuit can flexibly implement two different encoding schemes in one hardware implementation. E.g. a first encoding scheme may be applied to provide a highly linear DAC while a second encoding scheme may be applied to save power consumption.

In a first possible implementation form of the DAC circuit according to the first aspect, the first encoding scheme is a fully differential encoding scheme, and the second encoding scheme is a pseudo-differential encoding scheme.

This provides the advantage that by applying the fully differential encoding scheme, the DAC provides a highly linear result while by applying the pseudo-differential encoding scheme, the DAC operates in a power efficient manner. In a second possible implementation form of the DAC circuit according to the first aspect as such or according to the first implementation form of the first aspect, each conversion cell is configured to adopt a ternary output state comprising a high state, a low state and a zero state when the second encoding scheme is selected, wherein the ternary output state is based on a switching state of the switches of the conversion cell.

This provides the advantage that by using these three states, the pseudo-differential encoding scheme can be efficiently realized in which a zero output signal can be generated by turning off the switches of both subcells which results in reduced power consumption.

In a third possible implementation form of the DAC circuit according to the second implementation form of the first aspect, each conversion cell is configured to adopt only two of the three output states at any given time.

Hence, for the second encoding scheme, e.g. the pseudo-differential encoding scheme, to represent positive RF-DAC output only high and zero output states of conversion cells will be used, and to represent a negative RF-DAC output only low and zero output states of conversion cells will be used. The high and low states are not simultaneously allowed at a given time. This way, the waste in power consumption of the RF-DAC can be minimized, since positive and negative conversion cell contributions will never cancel each other at the RF-DAC output.

In a fourth possible implementation form of the DAC circuit according to any of the second or third implementation forms of the first aspect, each conversion cell is configured to: generate a positive output signal when a first subcell of the conversion cell is turned on and a second subcell of the conversion cell is turned off, generate a negative output signal when the first subcell is turned off and the second subcell is turned on, and generate a zero output signal when both subcells of the conversion cell are turned off.

This provides the advantage that for the second encoding scheme, e.g. the pseudo- differential encoding scheme, to represent a zero RF-DAC output zero output states of conversion cells will be used, i.e. both conversion cells are turned off. This results in a low power consumption. In a fifth possible implementation form of the DAC circuit according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the digital encoder is configured to turn on always one and only one subcell of a conversion cell when the first encoding scheme is selected.

This provides the advantage that for the first encoding scheme, e.g. the fully differential mode, a low (or -1 ) output will be achieved if the n subcell is turned on and a high (or +1 ) output will be achieved if the p subcell is turned on. There are no other outputs or switch configurations allowed in the fully differential mode. Hence, the output can be generated at high precision.

In a sixth possible implementation form of the DAC circuit according to the fifth

implementation form of the first aspect, each conversion cell is configured to adopt a differential output state comprising a high state and a low state when the first encoding scheme is selected, wherein the differential output state is based on a switching state of the switches of the conversion cell.

This provides the advantage that for the first encoding scheme, e.g. the fully differential mode, the DAC circuit can operate at high precision due to compensation of bias in the differential mode.

In a seventh possible implementation form of the DAC circuit according to the sixth implementation form of the first aspect, each conversion cell is configured to: generate a positive output signal when a first subcell of the conversion cell is turned on and a second subcell of the conversion cell is turned off, and generate a negative output signal when the first subcell is turned off and the second subcell is turned on.

This provides the advantage that these states of the conversion cell can be simply adjusted by the encoder.

In an eighth possible implementation form of the DAC circuit according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, a first subcell of the pair of subcells comprises a first current source configured to generate a first current; and a second subcell of the pair of subcells comprises a second current source configured to generate a second current, wherein a total output current at the DAC circuit is formed by adding contributions from all the first current sources of the first subcells and subtracting contributions from all the second current sources of the second subcells. This provides the advantage that such current sources can be efficiently realized by using transistors.

In a ninth possible implementation form of the DAC circuit according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, each subcell comprises a first transistor forming the switch and a second transistor forming the current source.

This provides the advantage that such a DAC circuit can be efficiently implemented by using common transistor logic.

In a tenth possible implementation form of the DAC circuit according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the DAC circuit comprises a controller configured to control the digital encoder selecting the first encoding scheme or the second encoding scheme.

This provides the advantage that the controller can be used to flexibly switch between the first and the second encoding schemes. The controller can also be used to flexibly implement other encoding schemes. In an eleventh possible implementation form of the DAC circuit according to the tenth implementation form of the first aspect, the controller is configured to control the digital encoder based on linearity and/or power requirements.

This provides the advantage that DAC circuit can operate as high-precision converter or as power-saving converter depending on the specific requirements. The controller can switch the different operation modes of the DAC circuit on-the-fly.

In a twelfth possible implementation form of the DAC circuit according to any of the tenth or eleventh implementation forms of the first aspect, the controller is configured to set part of the conversion cells to zero, in particular during backoff. This provides the advantage that further power can be saved, for example in backoff situations, when some or all of the conversion cells are set to zero. In a thirteenth possible implementation form of the DAC circuit according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the digital encoder is configured to selectively generate the digitally encoded output signal according to a third encoding scheme in which each conversion cell is configured to simultaneously adopt a high state, a low state and a zero state.

This provides the advantage that a higher flexibility can be achieved for implementing other modes of operation when further encoding schemes are implemented by the encoder. Hence, a compromise between power consumption of pseudo and fully differential modes can be obtained.

According to a second aspect, the invention relates to a digital transmitter circuit, comprising: a modulator circuit, configured to modulate a radio signalto provide a digital input signal; and a DAC circuit according to the first aspect as such or according to any of the implementation forms of the first aspect, configured to convert the digital input signal to an analog output signal.

Such a digital transmitter utilizes a DAC, e.g. an RF-DAC, providing trade-off between high linearity and reduced power consumption. The digital transmitter can flexibly transmit according to different different encoding schemes providing trade-off between linearity and power consumption.

According to a third aspect, the invention relates to a method for digital-to-analog conversion by a digital-to-analog converter (DAC) circuit comprising a digital encoder and a plurality of conversion cells, wherein each conversion cell comprises a pair of subcells and each subcell comprises a current source and a switch which is configured to switch the corresponding current source to an output of the subcell, the method comprising: generating, by the digital encoder, a digitally encoded output signal for controlling the switches of the pair of subcells of the conversion cells, wherein the digitally encoded output signal is selectively generated according to a first encoding scheme or according to a second encoding scheme. Such a method for digital-to-analog conversion can flexibly implement two different encoding schemes in one hardware implementation of a DAC. A first encoding scheme may be applied to provide high linearity while a second encoding scheme may be applied to provide reduced power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS Further embodiments of the invention will be described with respect to the following figures, in which:

Fig. 1 shows a block diagram illustrating the basic structure of a digital-to-analog converter (DAC) circuit 100 according to an implementation form;

Figs. 2a, 2b, 2c show circuit diagrams illustrating a current cell 103 of the DAC circuit 100 of Fig. 1 in different output states;

Fig. 3 shows a non-linear output impedance model 300 for the entire DAC circuit 100 of Fig. 1 according to an implementation form;

Figs. 4a and 4b show diagrams 400a, 400b illustrating integral non-linearity (INL) for a fully differential (Fig. 4a) and a pseudo-differential RF-DAC (Fig. 4b) implementation; Fig. 5 shows output spectra 500 for a fully differential 502 and a pseudo-differential 501 RF-DAC implementation for a sine wave; and

Fig. 6 shows output spectra 600 of a fully differential 602 and a pseudo-differential 601 RF- DAC implementation for a 20 MHz LTE signal.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

Fig. 1 shows a block diagram illustrating the basic structure of a digital-to-analog converter (DAC) circuit 100 according to an implementation form.

In Fig. 1 a simplified internal structure of RF-DAC 100 along with a digital encoder 105 is shown. The RF-DAC 100 is made of conversion cells 103 (one 103 of multiple conversion cells is exemplary highlighted in Fig. 1 ), where each cell 103 is divided into the p and n subcells 110, 120. The general structure of the subcells 110, 120 is similar and although there can be mismatches among the subcells 110, 120, they can be ignored hereinafter.

The current source 111 , 121 is the basic conversion element here, implemented e.g. by using CMOS transistors, and can be connected or disconnected from output 113, 123 by means of switches 112, 122, which again can be implemented e.g. by using CMOS transistors. The current I of the source 111 , 121 is proportional to the arbitrary weight assigned to the conversion cell 103 inside a given RF-DAC implementation. The switches 112, 122 are turned on or off by the digital encoder's 105 output signal 106. Please note that the position of current source 111 , 121 and switch 112, 122 is not strictly limited to the schematic shown in Fig. 1 , but they can be swapped. Also important is the fact that it is not necessary to implement the p subcell 110 and n subcell 120 current sources separately, they can be joined together as one single current source. The hardware used in conversion cell 103 depicted in Fig. 1 is in principle the same, for both the fully differential and pseudo differential RF-DACs. The only differences lie in the digital encoding (by the output signal 106 of the digital encoder 105) and the use of switches 112, 122.

The output 113, 123, as shown in Fig. 1 , is obtained by the differential combination of all the parallel p-subcells 110 and all the parallel n-subcells 120 with positive and negative terminals as indicated. The RF-DAC 100 is implemented and used in both configurations (referred to as encoding schemes 101 , 102), e.g. as pseudo differential or as fully differential as described in the following. The digital-to-analog converter (DAC) circuit 100 depicted in Fig. 1 includes a digital encoder 105 and a plurality of conversion cells 103. Each conversion cell 103 includes a pair of subcells 110, 120. Each subcell (e.g. subcell 110) includes a current source 111 and a switch 112 which is configured to switch the corresponding current source 111 to an output 113 of the subcell 110. The digital encoder 105 is configured to generate a digitally encoded output signal 106 for controlling the switches 112, 122 of the pair of subcells 110, 120 of the conversion cells 103. The digital encoder 105 is configured to selectively generate the digitally encoded output signal 106 according to a first encoding scheme

101 , e.g. a fully differential encoding scheme or according to a second encoding scheme

102, e.g. a pseudo-differential encoding scheme.

Each conversion cell 103 may adopt a ternary output state including a high state, a low state and a zero state when the second encoding scheme 102 is selected. The ternary output state is based on a switching state 201 , 202, 203, 204 of the switches 112, 122 of the conversion cell 103. Each conversion cell 103 may be configured to adopt only two of the three output states at any given time.

Each conversion cell 103 may be configured to: generate a positive output signal 113, 123 when a first subcell 110 of the conversion cell 103 is turned on 204 and a second subcell 120 of the conversion cell 103 is turned off 201 , e.g. as shown below in Fig. 2a; to generate a negative output signal 113, 123 when the first subcell 110 is turned off 203 and the second subcell 120 is turned on 202, e.g. as shown below in Fig. 2c; and to generate a zero output signal 113, 123 when both subcells 110, 120 of the conversion cell 103 are turned off 203, 201 , e.g. as shown below in Fig. 2b. The digital encoder 105 may be configured to turn on always one and only one subcell 110, 120 of a conversion cell 103 when the first encoding scheme 101 is selected. Each conversion cell 103 may be configured to adopt a differential output state comprising a high state and a low state when the first encoding scheme 101 is selected, wherein the differential output state is based on a switching state 201 , 202, 203, 204 of the switches

112, 122 of the conversion cell 103.

Each conversion cell 103 may be configured to: generate a positive output signal 113, 123 when a first subcell 110 of the conversion cell 103 is turned on 204 and a second subcell 120 of the conversion cell 103 is turned off 201 , and generate a negative output signal

113, 123 when the first subcell 110 is turned off 203 and the second subcell 120 is turned on 202.

A first subcell 110 of the pair of subcells 110, 120 may include a first current source 111 configured to generate a first current. A second subcell 120 of the pair of subcells 110, 120 may include a second current source 121 configured to generate a second current. A total output current at the DAC circuit may be formed by adding contributions from all the first current sources 111 of the first subcells 110 and subtracting contributions from all the second current sources 121 of the second subcells 120.

Each subcell 110, 120 may include a first transistor forming the switch 112, 122 and a second transistor forming the current source 111 , 121 .

The DAC circuit 100 may include a controller configured to control the digital encoder 105 selecting the first encoding scheme 101 or the second encoding scheme 102. The controller may be configured to control the digital encoder 105 based on linearity and/or power requirements. The controller may be configured to set part of the conversion cells 103 to zero, in particular during backoff. The digital encoder 105 may be configured to selectively generate the digitally encoded output signal 106 according to a third encoding scheme in which each conversion cell 103 is configured to simultaneously adopt a high state, a low state and a zero state.

Figs. 2a, 2b, 2c show circuit diagrams illustrating a current cell 103 of the DAC circuit 100 of Fig. 1 in different output states. The depicted current cells 103 represent current cells 103 as depicted in Fig. 1 which are in different states. In order to better understand the difference between fully differential and pseudo differential RF-DACs consider the current cell 103 depicted in Figs. 1 and 2. For the fully differential case always one and only one of the conversion subcells 110, 120 will be turned on, as controlled by the digital encoder 105 output 106. Hence, a low (or -1 ) output will be achieved if the n subcell 120 is turned on 202 and a high (or +1 ) output will be achieved if the p subcell 110 is turned on 204. There are no other outputs or switch configurations allowed in the fully differential mode.

For the pseudo differential case, another switch configuration is added. Now both the switches 112, 122 can be turned off 203, 201 . Hence a pseudo differential RF-DACs conversion cell 103 has three output possibilities. These possibilities, as shown in Figure 2, are: low (or -1 ) output with n subcell 120 turned on 202, high (or +1 ) output with p subcell 110 turned on 204 and zero output with neither one of the subcells 110, 120 turned on, i.e. both subcells 110, 120 turned off 203, 201 . Again the switches 112, 122 are controlled by the digital encoder 105 output 106.

In the scope of this disclosure, the pseudo differential encoding uses only two of the three allowed conversion cell 103 output states at any given time. Hence, to represent positive RF-DAC output 113, 123 only high and zero output states of conversion cells 103 are used, and to represent a negative RF-DAC output only low and zero output states of conversion cells 103 are used. The high and low states are not simultaneously allowed at a given time. This way, the waste in power consumption of the RF-DAC can be minimized, since positive and negative conversion cell contributions will never cancel each other at the RF-DAC output 113, 123. In the previous description there was a brief mention of the linearity and power

consumption trade-off between the fully differential and pseudo differential RF-DACs. From the above discussion it is quite clear that the power consumed in the pseudo differential RF-DAC will be smaller than the power consumed in the fully differential RF- DAC, due to the ability of pseudo differential RF-DAC to produce zero output states in the conversion cells if their direct contribution is not required. This ability is lacking in the fully differential RF-DACs. The power saved, as already mentioned, will be same as the PAPR of the input for a full-scale input signal.

Next, a detailed analysis of non-linearity on the fully differential and pseudo differential RF-DACs are presented. This analysis is relevant due to the fact that real current sources, in any implementation technology, have finite conductances associated with them. These conductances are a major cause of non-linear behavior and can be modeled as on and off conductances referring to the current source conductance when it is switched on or off respectively.

Fig. 3 shows a non-linear output impedance model 300 for the entire DAC circuit 100 of Fig. 1 according to an implementation form. In this impedance model 300 all the conversion cells are taken into account. In the impedance model 300, a contribution of the p subcells 110 can be modeled by a parallel circuit of a first impedance element 315 of (N- n P )G 0 ff, a current source 314 of n p LSB, a second impedance element 313 of n p G ON and a third impedance element 311 of RL/2. A contribution of the n subcells 120 can be modeled by a parallel circuit of a first impedance element 325 of (N-n M )G 0 ff, a current source 324 of ΠΜ I LSB, a second impedance element 323 of n M G ON and a third impedance element 321 of

In the simple non-linear output impedance model for the RF-DAC of Fig. 1 , as shown in Fig. 3, it is assumed that all the conversion cells, in a given RF-DAC implementation, have the same unity weight. A cell with weight K will be modeled as K cells with weight 1 , where:

R L = Load Resistance

GON = On Conductance of conversion cell

GOFF = Off Conductance of conversion cell

ILSB = LSB current

N = Total number of conversion cells

n P = Conversion cells switched to high output

n M = Conversion cells switched to low output A simple network analysis assuming no frequency dependence of conductances leads to:

For the fully differential case, since all the conversion cells are either set to high or low output, it can be simply assumed that:

This results in a differential current of:

Here it is quite clear that the differential current depends on the off and on conductances in an inverse squared manner. Even when the conductances are not squared they are being multiplied resulting in the second order conductance dependence. The conductance values in practice are small and their square or multiplication will result in an even smaller values. Hence the fully differential RF-DAC is weakly affected by the non-linear behavior.

For the case of pseudo differential RF-DAC, at a given time, conversion cells will either have high or low output in conjunction with zero output. Both the high and low outputs can't exist simultaneously, at a given time. Hence, if assuming a positive RF-DAC output, one gets:

This results in a differential current of:

Here it is quite clear that the differential current depends on the off and on conductances in an inverse proportionality with no squares involved. Hence the pseudo differential same signed RF-DAC is more strongly affected by the non-linear behavior. Figs. 4a and 4b show diagrams 400a, 400b illustrating integral non-linearity (INL) for a fully differential (Fig. 4a) and a pseudo-differential RF-DAC (Fig. 4b) implementation.

The above discussion of non-linearity affecting the pseudo differential RF-DAC more severely can be verified with the help of Integral non linearity (INL) simulations of both the RF-DACs. Figures 4a and 4b show the INL of fully differential (Fig. 4a) and pseudo differential (Fig. 4b) RF-DACs with finite output resistance and INLs normalized to LSB. The simulations were carried out using a 10 bit RF-DAC, where the two encoding schemes were implemented according to the description above. The non-linear model values used here are typical of CMOS implementations of the RF- DAC, and are given as:

It is quite clear from Figures 4a and 4b, especially by looking at the vertical axis scales, that pseudo differential RF-DAC is much more severely affected by the non-linearity.

As a verification of the proper operation of the pseudo differential same signed RF-DAC and as a means to compare it to the fully differential one, two sets of simulations were carried out. In both of the sets, a 10 bit RF-DAC with non-linear model values same as the ones stated above, was used. The digital encoder used was capable of supporting both the fully differential and pseudo differential RF-DACs, as described above in this disclosure.

In the first case, a full scale sine wave with a frequency of 9.501 MHz sampled at 921 .6 MHz was used as input. Figure 5 shows the output for both the fully differential 502 and pseudo differential 501 RF-DACs. Fig. 5 shows output spectra 500 for a fully differential 502 and a pseudo-differential 501 RF-DAC implementation for a sine wave.

It is quite clear from Figure 5 that the pseudo differential RF-DAC output 501 has higher odd-order harmonic distortion (at 3, 5, 7 times the sine frequency) than the fully differential RF-DAC output 502, and hence confirms the above discussion of higher non-linearity for the pseudo differential case.

In the second case, LTE (Long Term Evolution) signal of bandwidth 20 MHz was used as input. Figure 6 shows the output for both the fully differential 602 and pseudo differential 601 RF-DACs. Fig. 6 shows output spectra 600 of a fully differential 602 and a pseudo- differential 601 RF-DAC implementation for a 20 MHz LTE signal.

Again it can be seen from Figure 6 that pseudo differential RF-DAC 601 has worse ACLR (Adjacent Channel Leakage Ratio) value than the fully differential RF-DAC 602, therefore pointing towards a more non-linear behavior.

Figures 4 to 6 confirm the discussions above about the more non-linear behavior of pseudo differential RF-DAC when compared to the fully differential one.

Further generalizations can be applied: The same technique described here can be applied to baseband DACs as well. The RF-DAC is not always fed with full-scale signals, but sometimes the input signal is scaled down to allow for backoff operation. Even in fully differential mode, part of the conversion cells can be set to constant 0 during backoff, in order to save power. Besides pseudo and fully differential, other modes of operation are possible, where all three conversion cell states -1 , 0, +1 are allowed simultaneously. This may represent a compromise between the power consumption of pseudo and fully differential modes. The present disclosure also supports a method for digital-to-analog conversion by a digital-to-analog converter (DAC) circuit comprising a digital encoder and a plurality of conversion cells, wherein each conversion cell comprises a pair of subcells and each subcell comprises a current source and a switch which is configured to switch the corresponding current source to an output of the subcell. The method includes:

generating, by the digital encoder, a digitally encoded output signal for controlling the switches of the pair of subcells of the conversion cells, wherein the digitally encoded output signal is selectively generated according to a first encoding scheme or according to a second encoding scheme. The method allows performing the functionality of the DAC circuits 100, 200 as described above.

The present disclosure also supports a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the performing and computing steps described herein, in particular the steps of the method described above. Such a computer program product may include a readable non-transitory storage medium storing program code thereon for use by a computer. The program code may perform the method described above.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms "coupled" and "connected", along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be

appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the invention beyond those described herein. While the present invention has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.