Description

The present invention relates to a digital-to-analogue converter.

Microcontrollers are widespread and are frequently used to monitor, control or communicate with analogue signal devices.

Most microcontrollers have an integrated analogue-to-digital converter (ADC) module which allows them to convert an analogue input signal into a digital signal. However, many microcontrollers do not include an integrated digital-to-analogue converter (DAC) module.

Notwithstanding this, pulse-width modulation (PWM) can be used to implement a DAC using a microcontroller. A microcontroller timer module generates a PWM signal which is fed into an analogue low-pass filter resulting in an output signal, V _out , having a dc component. The dc voltage level of the output signal, V _out , is directly proportional to the duty cycle of the PWM signal. Thus, the microcontroller can adjust the dc voltage level by varying the duty cycle. Examples of PWM DACs are described in "PWM DAC Using MSP430 High-Resolution Timer", Texas Instruments Application Report SLAA497 (July 2011), "Using PWM Output as a Digital-to-Analog Converter on a TMS320F28OX Digital Signal Controller", Texas Instruments Application Report SPRAA88A (September 2008) and "Using PWM Timer_B as a DAC", Texas

Instruments Application Report SLAA116 (December 2000).

A PWM DAC has n-bit resolution, i.e. capable of providing 2" output levels, such that: where fcu is the frequency of a timer clock used to increment a timer counter and /PWM is the frequency of the PWM signal. Thus, DAC resolution can be increased by increasing/a and/or by decreasing^ W .

Although PWM can be used to implement a simple, low-cost DAC, PWM DACs generally suffer from having poor resolution and low bandwidth.

Case: 68865PCT1 DAC resolution can be lost due to ripple uncertainty particularly as /PWM decreases and approaches the filter cut-off frequency, fc. For example, if /CLK = 128 MHz,/™ = 2 MHz and c = 10 kHz, then a PWM DAC is expected to have a resolution of 6 bits.

Simulation of PWM DAC performance shows that the effective DAC resolution is about that expected. If PWM signal frequency, /PWM, is reduced by an order of magnitude to 200 kHz, then the PWM DAC is expected to exhibit a higher resolution, namely 9 bits. However, simulation shows that the effective DAC resolution is less than 3 bits, i.e. 6 bits below the expected DAC resolution. Voltage ripple and, thus, ripple uncertainty can be decreased by using a higher-order filter. However, this increases settling time of the filter, which can be as long as 1 second.

IffpwM is high (e.g. > lMHz) and a high resolution is desired (e.g. > 8 bits), then a timer clock frequency, /CLK, greater than 200 MHz is needed. However, most microcontrollers are not provided with such fast timers.

The present invention seeks to provide an improved DAC.

According to a first aspect of the present invention there is provided digital-to-analogue converter comprising a resistor having a resistance R and a capacitor having a capacitance C. The digital-to-analogue converter comprises a first switching element configured, in response to a first control signal, to couple the capacitor to a first rail (for example, a positive voltage supply rail) via a path having a resistance less than R and a second switching element configured, in response to a second control signal, to couple the capacitor to the first rail through the resistor. The digital-to-analogue converter comprises a third switching element configured, in response to a third control signal, to couple the capacitor to a second rail (for example, a ground rail) via a path having a resistance less than R and a fourth switching element configured, in response to a responsive to a fourth control signal, to couple the capacitor to the second voltage rail through the resistor. Thus, the capacitor can be quickly charged or discharged over a period less than RC or less than 0.7 RC.

The digital-to-analogue converter may comprise a first control element configured to switch on the second switching element before switching on the first switching element and a second control element configured to switch on the fourth switching element before switching on the third switching element.

Switching on the second switching element before the first switching element and switching on the fourth switching element before the second switching element can help to reduce or avoid a damaging current spike through the first and second switching elements when charging and discharging the capacitor respectively.

The first control element may switch on the second switching element at least 1 ns, at least 2 ns or at least 5 ns before switching on the first switching element. The first control element may switch on the second switching element no more than 50 ns, no more than 20 ns or no more than 10 ns before switching on the first switching element.

The second control element may switch on the fourth switching element at least 1 ns, at least 2 ns or at least 5 ns before switching on the third switching element. The second control element may switch on the fourth switching element no more than 50 ns, no more than 20 ns or no more than 10 ns before switching on the third switching element.

The first control element may be configured to switch on the second switching element before switching on the first switching element when the first control element is in a first state (e.g. an UP state) and the second control element may be configured to switch on the second switching element before switching on the first switching element when the second control element is in a second state (e.g. a DOWN state). The digital-to-analogue converter can provide high resolution, for example at least 8 bits, even if a timer clock frequency of 64 MHz is used. The digital-to-analogue converter can exhibit a settling time of less than 4 μβ and no more than 0.1% ripple at maximum output voltage. A control signal may be a HIGH pulse, i.e. going from LOW to HIGH (for a given duration) to LOW. A control signal may be a LOW pulse, i.e. going from HIGH to LOW (for a given duration) to HIGH.

The first switching element may be configured to couple the capacitor directly to the first rail. The third switching element may be configured to couple the capacitor directly to the second rail.

The digital-to-analogue converter may comprise a single capacitor between the first and second rails.

The first control element may be configured to provide the first control signal in dependence upon the second control signal (for example, a first timer signal, Ti) and a fifth control signal (for example, an adjust up signal, UP). The first control element may comprise a logic gate, for example, an OR gate.

The digital-to-analogue converter may comprise a first path between a control signal input (for example, an input for the second control signal) and a control terimanl of the first switching element (for example, a gate of a transistor) via an element which introduces a first delay (for example, the first control element) and a second path between the control signal input and a control terminal of the second switching element (for example, a gate of transistor) without an element which introduces a delay or via an element which introduces a delay less than the first delay.

The second control element may be configured to provide the third control signal in dependence upon the fourth control signal (for example, a second timer signal, T2) and a sixth control signal (for example, an adjust down signal, DOWN). The second control element may comprise a logic gate, for example an AND gate.

The digital-to-analogue converter may comprise a third path between another control signal input (for example, an input for the fourth control signal) and a control terimanl of the third switching element (for example, a gate of a transistor) via another element which introduces a second delay (for example, the second control element) and a fourth path between the control signal input and a control terminal of the fourth switching element (for example, a gate of transistor) without an element which introduces a delay or via an element which introduces a delay less than the second delay.

The first and second delays may be substantially the same duration. The first and second control elements may introduce first and second delays respectively. The first and/or second delay(s) may be at least 1 ns, at least 2 ns or at least 5 ns. The first and/or second propagation delay(s) may be no more than 50 ns, no more than 20 ns or no more than 10 ns. The first and third switching elements may be arranged in a push-pull configuration. The first and third switching elements may comprise first and third transistors. The first and third transistors may comprise bipolar junction transistors. The first and third switching elements may be of opposite types, e.g. one may be an npn transistor and the other may be a pnp transistor.

The second and fourth switching elements may be arranged in a push-pull

configuration. The second and fourth switching elements may comprise second and fourth transistors. The second and fourth transistors may comprise bipolar junction transistors. The second and fourth switching elements may be of opposite types, e.g. one may be an npn transistor and the other may be a pnp transistor. According to a second aspect of the present invention there is provided apparatus comprising the digital-to-analogue converter and a circuit arranged to provide or to cause generation of the control signals. A control signal is applied for a duration less than RC or less than 0.7 RC.

The circuit may comprise an integrated circuit. The integrated circuit may comprise a microcontroller.

According to third aspect of the present invention there is provided of controlling a digital-to-analogue converter comprising a resistor having a resistance R, a capacitor having a capacitance C and switch configured, in response to a control signal, to couple the capacitor to a rail (for example, a positive voltage supply rail, a negative voltage rail or to ground) through the resistor, the method comprising applying the control signal for a duration less than RC.

The method may comprise, when the capacitor is in a discharged state, initially charging the capacitor through the resistor for a given time period and then charging the capacitor via a path having a resistance less than R and, when the capacitor is in charged state, initially discharging the capacitor through the resistor for a given time period and then charging the resistor via a path having a resistance less than R

The path having a resistance less than R is preferably provided in parallel with the resistor. The charged state may be a partially-charged state.

The given time period may be at least 1 ns, at least 2 ns or at least 5 ns. The given time period may be no more than 50 ns, no more than 20 ns or no more than 10 ns. The method may comprise applying the control signal for a duration less than 0.7RC.

The digital-to-analogue converter may comprises a first switching element configured, in response to a first control signal, to couple the capacitor to a first rail via a path having a resistance less than R, a second switching element configured, in response to a second control signal, to couple the capacitor to the first voltage rail through the resistor, a third switching element configured, in response to a third control signal, to couple the capacitor to a second rail via a path having a resistance less than R, and a fourth switching element configured, in response to a fourth control signal, to couple the capacitor to the second rail through the resistor, wherein the method may comprises applying the first, second, third or fourth control signal for a duration less than RC.

Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure l shows a circuit including a capacitor C for generating an analogue output voltage, a resistor R9 and first, second, third and forth transistors Qi, Q2, Q3, Q4 used to charge and discharge the capacitor C;

Figure 2 is a table showing timer signal states and adjust signal states, output voltage responses and transistor states for the circuit shown in Figure 1;

Figure 3 is a table listing times and output voltages when charging and discharging the capacitor C through the resistor R9 shown in Figure 1;

Figure 4 is a graph showing output voltages against time;

Figure 5 is a graph showing output voltages against time;

Figure 6 is a schematic block diagram of the circuit shown in Figure 1 and a

microcontroller;

Figure 7 is a timing chart illustrating a first method of operation of the circuit shown in Figure 1;

Figure 8 is a schematic block diagram of the circuit shown in Figure 1 and a

microcontroller;

Figure 9 is a timing chart illustrating a second method of operation of the circuit shown in Figure 1;

Figure 10 shows plots of input and output signals for an OR gate illustrating

propagation delay;

Figure 11 shows plots of measured responses of the combined output of the first and second transistors and the capacitor shown in Figure 1 when charging from oVto 0.5 V; Figure 12 shows plots of measured responses of the combined output of the first and second transistors and the capacitor shown in Figure 1 when charging from oVto 0.5 V; Figure 13 shows plots of responses of the combined output of the first and second transistors and the capacitor shown in Figure 1 when charging from oV to 1.25 V;

Figure 14 shows plots of measured responses of the combined output of the first and second transistors and the capacitor shown in Figure 1 when charging from oV to 2.5 V; Figure 15 shows plots of measured responses of the combined output of the first and second transistors and the capacitor shown in Figure 1 when charging from oVto 2.5 V and adjusted by the second transistor;

Figure 16 shows plots of measured responses of the combined output of the first and second transistors and the capacitor shown in Figure 1 when charging from oV to 3.75 V; Figure 17 shows plots of measured responses of the combined output of the first and second transistors and the capacitor shown in Figure 1 when charging from oVto 3.75 V;

Figure 18 shows plots of measured responses of the combined output of the first and second transistors and the capacitor shown in Figure 1 when charging from oV to 4.5 V; Figure 19 shows plots of measured responses of the combined output of the first and second transistors and the capacitor shown in Figure 1 when charging from oVto 4.5 V and adjusted by the second transistor; and

Figure 20 shows plots of measured responses of the first, transistor, second transistor and the capacitor shown in Figure 1 when charging and discharging.

In the following description, like parts are denoted by like reference numerals. Referring to Figure 1, a circuit 1 is shown for implementing a DAC.

The circuit 1 includes first and second timer signal input terminals 2, 3 which receive first and second timer signals Τι, T2, first and second switch up and switch down selection signal input terminals 4, 5 which receive switch up and switch down selection signals UP, DOWN and an analogue signal output terminal 6 which provides an analogue signal VOUT.

The timer signals Τι, T2 (in this case, 16-bit timer signals) can be generated by an external timer using a timer clock having a frequency, /CLK, of 64 MHz. With a timer period of 16 μβ, 10-bit resolution can be achieved. The external timer can be provided by a microcontroller.

The first timer input terminal 2 and the switch up terminal 4 are connected to the inputs of a 2-input OR gate Ui. The second timer input terminal 3 and the switch down terminal 5 are connected to the inputs of a 2-input AND gate U2. The OR gate Ui takes the form of a Fairchild Semiconductor (RTM) TinyLogic (RTM) ultra high speed two- input OR gate (NC7SZ32) and the AND gate U2 takes the form of a Fairchild

Semiconductor (RTM) TinyLogic (RTM) high speed two-input AND gate (NC7S08). The OR and AND gates Ui, U2 have respective propagation times, t _PL i, t _PL2 . The output of the OR gate Ui is connected via a first resistor Ri to the base of a first transistor Qi in the form of a pnp bipolar transistor. The base of the first transistor Qi is pulled up to supply voltage, Vcc, via a second resistor R2. In this case, the supply voltage Vcc is 5 V. The emitter of the first transistor Qi is tied to the supply voltage, Vcc. The first transistor Qi takes the form of a Fairchild Semiconductor (RTM) PNP Epitaxial Silicon Transistor (BC327). The first resistor Ri has a resistance value of 510 Ω and the second resistor R2 has a resistance value of 90 Ω.

The first timer input terminal 2 is connected via a third resistor R3 to the base of a second transistor Q2 in the form of a pnp bipolar transistor. The base of the second transistor Q2 is pulled up to supply voltage, Vcc, via a fourth resistor R4. The emitter of the second transistor Q2 is tied to the supply voltage, Vcc. The second transistor Q2 takes the form of a Fairchild Semiconductor (RTM) PNP Epitaxial Silicon Transistor (BC327). The third resistor R3 has a resistance value of 510 Ω and the fourth resistor R4 has a resistance value of 90 Ω.

The output of the AND gate U2 is connected via fifth resistor R5 to the base of a third transistor Q3 in the form of an npn bipolar transistor. The base of the third transistor Q3 is pulled down to ground via a sixth resistor R6. The emitter of the third transistor Q3 is tied to ground. The third transistor Q3 takes the form of a Fairchild

Semiconductor (RTM) PNP Epitaxial Silicon Transistors (BC337). The fifth resistor R5 has a resistance value of 510 Ω and the sixth resistor R6 has a resistance value of 90 Ω.

The second timer input terminal 3 is connected via a seventh resistor R7 to the base of a fourth transistor Q4 in the form of an npn bipolar transistor. The base of the forth bipolar transistor Q4 is pulled down to ground via an eighth resistor R8. The emitter of fourth transistor Q4 is tied to ground. The fourth transistor Q4 takes the form of a Fairchild Semiconductor (RTM) PNP Epitaxial Silicon Transistors (BC337). The seventh resistor R7 has a resistance value of 510 Ω and the eighth resistor R8 has a resistance value of 90 Ω.

The first and third transistors Qi, Q3 are arranged in series in a totem pole

configuration, without any pull up or pull down resistors, between a first rail 7 which is connected to positive supply voltage Vcc and second rail 8 which is connected to ground GND. The second rail 8 can be connected to negative supply voltage V _E E instead of ground GND. The collectors of the first and third transistors Qi, Q3 are connected at a first node 9. The first node 9 is connected to a second node 10 which is connected to the output terminal 6.

The second and fourth transistors Q2, Q4 are arranged in series in a totem pole configuration, without any pull up or pull down resistors, between the first and second rails 7, 8. The collectors of the second and fourth transistors Q2, Q4 are connected at a third node 11. The second and third nodes 10, 11 are connected via a ninth resistor R9. The ninth resistor R9 has a resistance value of 510 Ω. A capacitor C is connected between the second node 10 and a fourth node 12 which lies on or is connected to the second rail 8. The capacitor C has a capacitance value of 22 pF.

Referring also to Figure 2, output of the capacitor C can be switched up to Vcc by the first and second transistors Qi, Q2 switching ON and can be switched down to oV by third and fourth transistors Q3, Q4 switching ON. The propagation delays through the OR gate Ui and AND gate U2 allows the second and fourth transistors Q2, Q4 to switch ON earlier than (approximately 9 ns before) the first and third transistors Qi, Q3 and so avoid a damaging current spike through the first and third transistors Qi, Q3.

As will be explained in more detail hereinafter, in switch up and switch down modes, the first and third transistors Qi, Q3 can be used to achieve a very quick transition (of the order of a few microseconds) to Vcc or to oV. In adjustment mode, the second and fourth transistors Q2, Q4 are used to adjust the output voltage, VOUT, at output terminal 6 to the required level.

Referring to Figures 1, 3 and 4, the largest change in voltage across the capacitor C occurs when the capacitor C charges from oVto O.sVcc and when it discharges from Vcc

A first response curve 13 shows the voltage across the capacitor C as it is charged through the second transistor Q2 and ninth resistor R9. A second response curve 14 shows the voltage across the capacitor C as it is discharged through the fourth transistor Q4 and ninth resistor R9. A third response curve 15 shows the voltage across the capacitor C when it is charged by the first transistor Qi in switch up mode. A fourth response curve 16 shows voltage across the capacitor C when it is discharged by the third transistor Q3 in switch down mode.

The first response curve 13 is nearly linear when the capacitor C is charged from oV to O.sVcc. Likewise, the second response curve 14 is nearly linear when the capacitor C is discharged from Vcc to O.sVcc. This can be used to achieve a very fast transition time and a simple calculation can be used to calculate an ON time to achieve a required output voltage.

Charging and discharging to reach a required output voltage can be achieved in single charging or discharging cycle from a discharged or charged state. Charging is not dependant on charge integration over a multiple cycles. Once the required voltage has been achieved, the transistors Qi, Q2, Q3, Q4 are switched OFF, minimising charge drain from the capacitor C. The output voltage, VOUT, can be monitored and, if necessary, adjusted using the second and fourth transistors Q2, Q4.

To achieve a fast transition time, a small RC time constant is used. However, the value of capacitance is chosen not to be too small because for small values, charge leakage has a larger effect on the output voltage, VOUT, since V=Q/ C. Thus, the capacitance value of the capacitor C is chosen to be at least 15 pF.

The circuit 1 can be operated in two ways. Whichever method is used, the circuit 1 can be used to achieve a quick response. Charging / discharging occurs in a period lasting less than 0.7 RC. Thus, timer signals Τι, T2 and switch up and switch down signals are applied for periods less than 0.7 RC. In this case RC = 11 μβ. The circuit 1 also benefits from little ripple voltage. First method of operation

A first method of operating the circuit 1 will be explained with reference to Figure 5.

Referring to Figure 5, if a voltage V _A is required which lies between oV and O.sVcc, then the capacitor C is reset, i.e. completely discharged by switch down, and then charged to reach the required voltage V _A following path 17. If a voltage V _B is required which lies between o.sVcc and Vcc, then the capacitor C is set, i.e. charged to Vcc by switch up, and then discharged to the required voltage V _B following path 18.

Apparatus for controlling the circuit 1 using the first method of operation will now be described with reference to Figures 6 and 7.

Referring to Figure 6, the circuit 1 can be controlled using a microcontroller 20 which generates first and second timer signals Ti, T2 and first and second switch up and switch down signals UP, DOWN. The DEFAULT and ACTIVE values of the first timer signal Ti are HIGH and LOW respectively. The DEFAULT and ACTIVE values of the second timer signal T2 are LOW and HIGH respectively.

The microcontroller 20 includes first and second timer signal output terminals 21, 22 which supply the first and second timer signals Ti, T2 and first and second general purpose digital input/output terminals 23, 24 which supply the switch up and switch down signals UP, DOWN. The timer module 26 generates the first and second timer signals Ti, T2 which are output via timer signal output terminals 21, 22 and supplied to the first and second timer input terminals 2, 3 of the DAC circuit 1. The microcontroller 20 may be, for example, a member of the Renesas Electronics (RTM) RL 78 (RTM) family, such as the RL78/I1A.

The microcontroller 20 includes a central processing unit (CPU) 25 running application software (not shown) and a timer module 26.

The CPU 25 controls the timer module 26 and generates appropriate switch up and switch down signals UP, DOWN.

Referring to Figures 1, 2, 6 and 7, operation of the circuit 1 and the microcontroller 20 will now be described.

In an initial state, the capacitor C is discharged and the analogue output signal VOUT is oV. When the first and second timer signals Ti, T2 have default values, i.e. HIGH and LOW values respectively, and the switch up and switch down signals UP, DOWN are LOW, then the transistors Qi, Q2, Q3, Q4 are OFF. Application software (not shown) sets a reference voltage VREF, for example 3.75 V (i.e. 0.75xVcc). The application software (not shown) determines that 3.75 V is greater than 0.5 x Vcc and so determines that the capacitor C should be first charged to Vcc using switch up and then partially discharged through the ninth resistor R9. Set (Vcc)

Under control of the application software (not shown), the CPU 25 resets (i.e. brings LOW) the first timer signal Ti and the switch up signal UP. Thus, the first and second transistors Qi, Q2 are switched ON. The second transistor Q2 is switched on slightly before the first transistor Qi due to propagation delay through the OR gate Ui. The first timer signal Ti and the switch up signal UP are kept LOW for a duration, t RESET, which is sufficiently long to charge capacitor C to Vcc. For example, tRESET = 5 μβ.

Adjust down

The CPU 25 calculates using a simple linear equation (not shown) or uses a look-up table (not shown) a duration, ti, of pulse needed to reduce the voltage across the capacitor by 1.25 V (i.e. 5V - 3.75 V).

The CPU 25 sets (i.e. drives HIGH) the second timer signal T2 for the duration, ti. Thus, the fourth transistor Q4 is switched ON which causes the capacitor C to start discharging. When the timer signal T2 is reset, discharging of the capacitor stops.

Application software (not shown) sets a reference voltage VREF, for example 0.25 V. The application software (not shown) determines that 0.25 V is less than 0.5 x Vcc and so determines that the capacitor C should be first discharged to oV using switch down and then partially charged through the ninth resistor R9.

Reset (oV)

Under control of the application software (not shown), the CPU 25 sets (i.e. brings HIGH) the second timer signal T2 and the switch down signal DOWN. Thus, the third and fourth transistors Q3, Q4 are switched ON. The second timer signal T2 and the switch down signal DOWN are kept LOW for a duration, tsET, which is sufficiently long to discharge the capacitor C to oV. For example, tsET = 5 μβ.

Adjust down

The CPU 25 calculates using a simple linear equation (not shown) or uses a look-up table (not shown) a duration, t ₂ , of pulse needed to charge the capacitor such that the voltage is 0.25 V.

The CPU 25 resets (i.e. brings LOW) the first timer signal Ti for the duration, t ₂ . Thus, the second transistor Q2 is switched ON which causes the capacitor C to start charging. When the timer signal Ti is returned to DEFAULT value (i.e. HIGH), charging of the capacitor ceases.

Thus, a required analogue voltage output VOUT can be achieved quickly, i.e. within a few microseconds.

A microcontroller need not be used. For example, a timer integrated circuit (not shown) and a logic circuit (not shown) may be used instead. Second method of operation

A second method of operating the circuit 1 is to employ rapid charging and discharging using switch up and switch down, i.e. to use switch up and switch down to charge and discharge the capacitor C partially without the need for setting or resetting (i.e fully charging or discharging) the capacitor C. For example, the second method can be used to charge the capacitor C from oV or from a low voltage (e.g. 0.5 V) to a value greater than 0.5VCC (e.g. 4.5V) directly. This is possible because the circuit 1 has a quick response. For example, the circuit 1 has a response time of 3.5 μβ for a transition from o V to 4.5 V. Apparatus for controlling the circuit 1 using the second method of operation will now be described with reference to Figures 8 and 9.

Referring to Figure 8, the circuit 1 is controlled using the microcontroller 20 using first and second timer signals Ti, T2 and first and second switch up and switch down signals UP, DOWN using the microcontroller 20. The DEFAULT and ACTIVE values of the first timer signal Ti are HIGH and LOW respectively. The DEFAULT and ACTIVE values of the second timer signal T2 are LOW and HIGH respectively.

The microcontroller 20 includes a central processing unit (CPU) 25 running application software (not shown), a timer module 26, a variable reference voltage module 27, a comparator 28 and an analog-to-digital converter (ADC) module 29. The ADC module 29 has a resolution which is the same or greater than the resolution the resolution as the DAC circuit. In this case, the ADC module 29 has 10-bit resolution. The microcontroller 20 includes an analogue signal input terminal 30.

The CPU 25 sets the required voltage and generates appropriate switch up and switch down signals UP, DOWN.

The CPU 25 sets the required voltage VREF using the variable reference voltage module 27 which is used to supply the analogue reference voltage VREF to the comparator 28. The comparator 28 generates an interrupt, TIMER STOP, which controls the timer module 26. The timer module 26 generates the first and second timer signals Ti, T2 which are output via timer signal output terminals 21, 22 and supplied to the first and second timer input terminals 2, 3 of the DAC circuit 1.

The timer module 26 is used to output a pulse with an ACIWE time calculated to achieve the required voltage.

To improve the accuracy of the DAC circuit 1, the analogue output voltage VOUT can be measured using the ADC module 29 and then adjusted to make any corrections.

The DAC circuit 1 ameliorates the problem of high ripple voltage without using high- order filters and offers a high resolution and fast settling times without the need for a very high frequency timer clock.

Referring to Figures 1, 2, 7 and 8, operation of the circuit 1 and microcontroller 20 will now be described.

In an initial state, the capacitor C is discharged and the analogue output signal VOUT is oV. When the first and second timer signals Ti, T2 have default values, i.e. HIGH and LOW values respectively, and the first and second switch up and switch down signals UP, DOWN are LOW, then the transistors Qi, Q2, Q3, Q4 are OFF. Switch up

Application software (not shown) sets a reference voltage VREF, for example 3.75 V (i.e. 0.75xVcc). Under control of the application software (not shown), the CPU 25 resets (i.e. brings LOW) the first timer signal Ti and the switch up signal UP and passes the value VREF to the variable reference voltage module 27. In response, the first and second transistors Qi, Q2 are switched ON (the second transistor Q2 is switched on slightly before the first transistor Qi) and the analogue output signal VOUT begins to increase.

The analogue output signal VOUT is fed back to the microcontroller 20 and is supplied to the comparator 28 and to the ADC module 29. The ADC module 29 polls VOUT and periodically supplies a digital value of the measurement to the CPU 25.

The output of the comparator 28 remains low while the analogue output signal VOUT and reference voltage signal VREF are unequal. Thus, the first timer Ti remains LOW.

When the analogue output signal VOUT equals the reference voltage signal VREF, the comparator 28 generates an interrupt in the form of a HIGH pulse which stops the first timer Ti, i.e. the first timer Ti is set (i.e. goes HIGH). Under control of the application software (not shown), the CPU 25 sets (i.e. brings HIGH) the switch up signal UP. Thus, the first and second transistors Qi, Q2 are switched OFF.

Adjust up

The ADC module 29 continues to poll the analogue output signal VOUT and the CPU 25 carries on monitoring the analogue output signal VOUT. If the CPU 25 determines that VOUT has dropped below a threshold value (due to the capacitor discharging), then the CPU 25 resets (i.e. brings LOW) the first timer signal Ti. In response, the second transistor Q2 is switched ON. The capacitor C is charged through the ninth requestor R9 so and the analogue output signal VOUT begins to increase. When the analogue output signal VOUT equals the reference voltage signal VREF, the CPU 25 stops the first timer Ti, thereby switching off the second transistor Q2. This process can continued to provide fine adjustment of the analogue output signal VOUT. Switch down

Application software (not shown) sets a new reference voltage VREF, for example 0.25 V (i.e. O.osxVcc). Under control of the application software (not shown), the CPU 25 sets (i.e. drives HIGH) the second timer signal T2 and the switch down signal DOWN and passes the value VREF to the variable reference voltage module 27. In response, the third and fourth transistors Q3, Q4 are switched ON (the fourth transistor Q4 is switched on slightly before the third transistor Q3) and the analogue output signal VOUT begins to decrease.

The analogue output signal VOUT is fed back to the microcontroller 61 and is supplied to the comparator 28 and to the ADC module 29. The ADC module 29 polls VOUT and periodically supplies a digital value of the measurement to the CPU 25.

The output of the comparator 28 remains low while the analogue output signal VOUT and reference voltage signal VREF are unequal. Thus, the first timer T2 remains HIGH.

When the analogue output signal VOUT equals the reference voltage signal VREF, the comparator 28 generates an interrupt in the form of a HIGH pulse which stops the second timer T2, i.e. the second timer T2 is reset (i.e. brought LOW). Under control of the application software (not shown), the CPU 25 resets (i.e. brings LOW) the switch down signal DOWN. Thus, the third and fourth transistors Q3, Q4 are switched OFF.

The ADC module 29 continues to poll the analogue output signal VOUT and the CPU 25 carries on monitoring the analogue output signal VOUT. If the CPU 25 determines that VOUT has dropped below a threshold value (due to the capacitor discharging), then the CPU 25 can adjust the analogue output signal VOUT as hereinbefore described.

When the analogue output signal VOUT equals the reference voltage signal VREF, the CPU 25 stops the first timer Ti, thereby switching off the second transistor Q2. This process can continued to provide fine adjustment of the analogue output signal VOUT.

Switch up and adjust down A combination of fast switching up and slow adjustment down can be used to reach a required voltage level.

Application software (not shown) sets a reference voltage VREF, for example 0.5 V (i.e. o.ixVcc). Under control of the application software (not shown), the CPU 25 resets (i.e. brings LOW) the first timer signal Ti and the switch up signal UP and passes the value VREF to the variable reference voltage module 27. In response, the first and second transistors Qi, Q2 are switched ON and the analogue output signal VOUT begins to increase.

The analogue output signal VOUT is fed back to the microcontroller 81 and is supplied to the comparator 28 and to the ADC module 29. The ADC module 29 polls VOUT and periodically supplies a digital value of the measurement to the CPU 25. The output of the comparator 28 remains low while the analogue output signal VOUT and reference voltage signal VREF are unequal. Thus, the first timer Ti remains LOW.

When the analogue output signal VOUT equals the reference voltage signal VREF, the comparator 28 generates an interrupt in the form of a HIGH pulse which stops the first timer Ti, i.e. the first timer Ti is set (i.e. goes HIGH). Under control of the application software (not shown), the CPU 25 sets (i.e. brings HIGH) the switch up signal UP. Thus, the first and second transistors Qi, Q2 are switched OFF.

If the CPU 25 determines that the analogue output signal VOUT has overshot, then it can use fine adjustment to reduce the value.

The CPU 25 sets (i.e. drives HIGH) the second timer signal T2. In response, the fourth transistor Q4 is switched ON. The capacitor C is discharged through the ninth requestor R9 so and the analogue output signal VOUT begins to decrease.

When the analogue output signal VOUT equals the reference voltage signal VREF, the CPU 25 stops the second timer T2, thereby switching off the fourth transistor Q4.

In this case, the voltage ripple arises due to the feedback loop time, i.e. not due to a filter circuit. The ripple voltage is small and is of the order of microvolts. Examples

Operation of the circuit l and microcontroller 20 will now be illustrated with reference to Figures 10 to 20. Figure 10 shows the input and output of the OR gate Ui (Figure 1). As shown in Figure 8, the output of the OR gate Ui (Figure 1) is delayed by approximately 7 ns compared to the input.

Figure 11 shows plots of voltage against time of the combined output of the first and second transistors Qi, Q2 and the voltage output, VOUT, when charging from oV to 0.5 V. As shown in Figure 9, voltage output, VOUT, increases while the first and second transistors Qi, Q2 are OFF and remains steady (with little ripple voltage) when the first and second transistors Qi, Q2 are ON. Figure 12 shows plots of voltage against time of the combined output of the first and second transistors Qi, Q2 and the voltage output, VOUT, when charging from oV to 0.5 V over a longer period of time.

Figure 13 shows plots of voltage against time of the combined output of the first and second transistors Qi, Q2 and the voltage output, VOUT, when charging from oV to 1.25 V.

As shown in Figure 13, voltage output, VOUT, increases linearly while the first and second transistors Qi, Q2 are OFF and remains steady, with little ripple when the first and second transistors Qi, Q2 are ON.

Figure 14 shows plots of voltage against time of the combined output of the first and second transistors Qi, Q2 and the voltage output, VOUT, when charging from oV to 2.5 V.

Figure 15 shows plots of voltage against time of the combined output of the first and second transistors Qi, Q2 and the voltage output, VOUT, when charging from oV to 2.5 V and adjusted by the second transistor. Figure 16 shows plots of voltage against time of the combined output of the first and second transistors Qi, Q2 and the voltage output, VOUT, when charging from oV to 3.75 V. Figure 17 shows plots of voltage against time of the combined output of the first and second transistors Qi, Q2 and the voltage output, VOUT, when charging from oV to 3.75 V over a longer period of time.

Figure 18 shows plots of voltage against time of the combined output of the first and second transistors Qi, Q2 and the voltage output, VOUT, when charging from oV to 4.5 V.

Figure 19 shows plots of voltage against time of the combined output of the first and second transistors Qi, Q2 and the analogue voltage output, VOUT, when charging from oV to 4.5 V and then adjusted by the second transistor Q2.

Figure 20 shows plots of voltage against time of the output of the first transistor 11, the output of the second transistor Q2 and the voltage output, VOUT, as the capacitor C is charged, set (i.e. switched up), discharged and reset (i.e. switched down).

It will be appreciated that many modifications may be made to the embodiments hereinbefore described.

The first, second, third and fourth transistors Qi, Q2, Q3, Q4 may be replaced by other forms of switching elements.

The first, second, third and fourth transistors Qi, Q2, Q3, Q4 need not be bipolar junction transistors. For example, one, more or all of the transistors Qi, Q2, Q3, Q4 may be metal-oxide-semiconductor field effect transistors (MOSFETs).

If the control signals are inverted, the conductivity types of the transistors Qi, Q2, Q3, Q4 can be inverted. For example, the first and third transistors Qi, Q3 can be npn transistors and the second and fourth transistors Q2, Q4 can be pnp transistors. The capacitor C may have another, different value, for example, up to 100 nF or more. The ninth resistor R9 may have a value other than 510 Ω and may have a value which is different from the first, third, fifth and/or seventh resistors Ri, R3, R5, R7.

The first, third, fifth and seventh resistors Ri, R3, R5, R7 may have values other than 510 Ω and need not all have the same values.

The second, fourth, sixth and eight resistors R2, R4, R6, R8 may have values other than 90 Ω and need not all have the same values. A resistor may be placed in the series with first transistor Qi, between the capacitor C and the first rail 7, provided that the resistor has a lower value than the resistance of the ninth resistor R9, for example, no more than half the value of the ninth resistor R9.

A resistor may be placed in the series with third transistor Q3, between the capacitor C and second rail 8, provided that the resistor has a lower value than the resistance of the ninth resistor R9, for example, no more than half the value of the ninth resistor R9.

The circuit can be controlled using a simple control circuit which includes a voltage reference which provides a voltage reference signal, a comparator which compares the voltage reference signal and the voltage output to provide a timer interrupt, a timer, for example a 555 timer, provides timer signals.

A logic gate need not be used to provide a propagation delay. A delay line (for example formed by RC elements), analog or digital elements may be used.