Title:
DIGITAL TRANSMIT PHASE TRIMMING
Document Type and Number:
WIPO Patent Application WO2006081096
Kind Code:
A8
Abstract:
A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs onto at least one second data line output data signals in accordance with a plurality of second clock signals. A timing measurement circuit determines at least one timing parameter of at least one output data signal on at least the one second data line and generates the control signal in accordance with a deviation of at least the one timing parameter from a desired value.
Inventors:
DALLY WILLIAM J (US)
Application Number:
PCT/US2006/001592
Publication Date:
August 30, 2007
Filing Date:
January 13, 2006
Export Citation:
Assignee:
RAMBUS INC (US)
DALLY WILLIAM J (US)
DALLY WILLIAM J (US)
International Classes:
H03M9/00; H04J3/06
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