Title:
DIGITALLY-CONTROLLED LOW-DROPOUT REGULATOR
Document Type and Number:
WIPO Patent Application WO/2020/250522
Kind Code:
A1
Abstract:
Provided is a digitally-controlled LDO regulator capable of controlling an output voltage even during an auto-zero processing period. The digitally-controlled low-dropout regulator comprises a plurality of AD converters and a variable impedance circuit. Each of the plurality of AD converters includes a comparator. A first signal from each of the plurality of AD converters is input to the variable impedance circuit. A second signal output from the variable impedance circuit is input to one of two terminals in each of the plurality of AD converters. While one of the plurality of AD converters is operating, the remaining AD converters among the plurality of AD converters execute auto-zero processing, and a voltage value serving as a reference is set. Each comparator compares a voltage value of the second signal input to the one terminal with the voltage value which has been set.
Inventors:
IDE DAISUKE (JP)
SHIGYO NOBUHIKO (JP)
KOMAGATA KEITA (JP)
WATANABE HIROYUKI (JP)
NAITO TAKAHIRO (JP)
SHIGYO NOBUHIKO (JP)
KOMAGATA KEITA (JP)
WATANABE HIROYUKI (JP)
NAITO TAKAHIRO (JP)
Application Number:
PCT/JP2020/011332
Publication Date:
December 17, 2020
Filing Date:
March 16, 2020
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G05F1/56
Foreign References:
| JP2010170470A | 2010-08-05 | |||
| US20060226898A1 | 2006-10-12 | |||
| JP2004194066A | 2004-07-08 | |||
| JP2016519356A | 2016-06-30 |
Attorney, Agent or Firm:
WATANABE Kaoru (JP)
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