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Title:
DISCRETE TIME ANALOG CIRCUIT AND RECEIVER USING SAME
Document Type and Number:
WIPO Patent Application WO/2012/014464
Kind Code:
A1
Abstract:
A discrete time analog circuit has a high degree of freedom in the zero-point and pole setting positions of a filter, and has wide band and steep filter characteristics. The discrete time analog circuit (100) is provided with: a rotate capacitor circuit (150); an amplifier (141) that is connected to the input line or the output line of the rotate capacitor (150), and amplifies the input potential or input charge; a coefficient circuit (140) that is positioned in series with the amplifier (141), and has two history capacitors (143-1, 143-2) positioned parallel to each other; a first active capacitor among the two history capacitors (143-1, 143-2) that is connected to and charges the amplifier (141); and a clock generation circuit (110) that is connected to the input line or the output line without the involvement of the amplifier (141), and that sequentially changes the pairing of the rotate capacitor circuit (150)a second active capacitor, which shares a charge with the rotate capacitor circuit (150).

Inventors:
SHIOZAKI, Hiroka (())
塩崎 泰翔 (())
ARAKI, Kiyomichi (())
荒木 純道 (())
Application Number:
JP2011/004239
Publication Date:
February 02, 2012
Filing Date:
July 27, 2011
Export Citation:
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Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真1006番地 Osaka, 〒5718501, JP)
SHIOZAKI, Hiroka (())
塩崎 泰翔 (())
ARAKI, Kiyomichi (())
International Classes:
H03H19/00; H03K17/00; H04B1/26; H04B1/30
Attorney, Agent or Firm:
WASHIDA, Kimihito (8th Floor, Shinjuku First West Bldg. 1-23-7, Nishi-Shinjuku, Shinjuku-k, Tokyo 23, 〒1600023, JP)
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Claims: